Taiwan Semiconductor Mfg Co Ltd v. Advanced Integrated Circuit Process LLC

1. Case Identification

• Case #: IPR2025-00829
• Patent #: 7,923,764
• Filed: April 15, 2025
• Petitioner(s): Taiwan Semiconductor Manufacturing Company Ltd.
• Patent Owner(s): Advanced Integrated Circuit Process LLC
• Challenged Claims: 1-21

2. Patent Overview

• Title: Semiconductor Device and Method for Fabricating the Same
• Brief Description: The ’764 patent relates to techniques for improving the performance and reliability of a Metal Insulator Semiconductor Field-Effect Transistor (MISFET). The invention focuses on a device structure where a high-dielectric-constant (high-k) gate insulating film extends from beneath the gate electrode to beneath an adjacent sidewall structure, with the film having a smaller thickness under the sidewall than under the gate electrode.

3. Grounds for Unpatentability

Ground 1: Obviousness over Matsumoto - Claims 1, 4-5, and 14-21 are obvious over Matsumoto.

• Prior Art Relied Upon: Matsumoto (Application # 2003/0025135).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Matsumoto’s first and fourth embodiments of a MOSFET device disclose all limitations of independent claim 1. Matsumoto teaches a semiconductor device with a high-k gate insulating film (film 6), a gate electrode (7), a first insulating sidewall (film 8, an oxide film), and a second insulating sidewall (film 9, a nitride film). Petitioner asserted that Matsumoto’s figures and fabrication process show the high-k film is continuously formed, extending from under the gate electrode to under the first insulating sidewall, and that it is thinner under this sidewall than under the gate electrode, thus rendering the claimed convex shape. Dependent claims were argued to be obvious as Matsumoto describes the first sidewall as an "offset insulation film" (claim 4) and discloses multi-layer sidewall structures (claims 14-15).
  • Motivation to Combine (for §103 grounds): While this ground relies on a single reference, Petitioner argued a person of ordinary skill in the art (POSITA) would have been motivated to use a high-k dielectric in Matsumoto’s device to address well-known problems associated with scaling silicon dioxide (SiO2) dielectrics.
  • Expectation of Success (for §103 grounds): A POSITA would have had a high expectation of success as Matsumoto explicitly suggests using high-k materials like Al2O3 or Ta2O5 for the gate insulating film.

Ground 2: Anticipation by Kajiyama - Claims 1, 5, 16-17, and 21 are anticipated by Kajiyama.

• Prior Art Relied Upon: Kajiyama (a certified translation of JP2003-258241).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner asserted that Kajiyama’s first embodiment FET anticipates every element of independent claim 1. Kajiyama discloses a gate electrode (3) on a high-k gate insulating film (2), with a first insulating sidewall (5, ZrO2) and a second insulating sidewall (6, Si3N4) formed on the gate electrode’s side surfaces. Petitioner contended that Kajiyama’s fabrication process, where the high-k film is etched along with the gate electrode, inherently results in a structure where the film is thicker under the gate than elsewhere. The process further shows the film extends continuously under the first sidewall but is removed from under the second sidewall, anticipating the limitations of claim 1 and dependent claim 5. The extended film structure was also argued to anticipate the width requirements of claims 16-17.

Ground 3: Obviousness over Matsumoto and Wang - Claims 2-3, 6-7, and 11 are obvious over Matsumoto in view of Wang.

• Prior Art Relied Upon: Matsumoto (Application # 2003/0025135) and Wang (Application # 2006/0131672).

• Core Argument for this Ground:

  • Prior Art Mapping: This combination addresses dependent claims requiring a "buffer insulating film" (claims 2-3) and specific high-k materials (claims 6-7) and thicknesses (claim 11), which Matsumoto does not explicitly disclose. Wang teaches a transistor with a thin dielectric layer (preferably silicon oxide) between the substrate and a high-k gate dielectric layer to improve device performance. Petitioner argued a POSITA would combine Wang's buffer layer with Matsumoto's device. Wang also discloses using Hf-based oxides like HfO2 and HfSiON (claims 6-7) and teaches depositing a HfSiON layer to a thickness of 0.5 to 5 nm, which overlaps with the "2 nm or less" limitation of claim 11.
  • Motivation to Combine (for §103 grounds): A POSITA would combine the references to improve Matsumoto's device performance. Wang explicitly stated that a buffer layer is used to mitigate undesirable interactions between high-k dielectrics and the underlying semiconductor substrate, thereby improving carrier mobility and reliability—a universal goal in the field.
  • Expectation of Success (for §103 grounds): Success would be expected and predictable, as incorporating a buffer layer was a known technique to improve MISFETs, and both references employed standard, compatible semiconductor fabrication processes.

• Additional Grounds: Petitioner asserted numerous additional grounds. These included challenges based on Matsumoto in view of other references (Sim, Mutou, Ono, Rodder, Bu, Wilk) to teach various dependent claim features, such as specific sidewall structures, pocket/extension regions, and material properties. A parallel set of grounds was asserted based on Kajiyama in combination with the same secondary references.

4. Arguments Regarding Discretionary Denial

• Petitioner argued against discretionary denial under 35 U.S.C. §314(a) by stipulating, pursuant to the Sotera decision, that if IPR is instituted, it will not pursue in the co-pending district court litigation any invalidity ground that was raised or reasonably could have been raised in the IPR.
• Petitioner argued against discretionary denial under 35 U.S.C. §325(d), contending that the Examiner did not consider the primary prior art references (Matsumoto and Kajiyama) during prosecution. Petitioner asserted these references teach the core structure of the independent claims, which the patent owner had argued was patentably distinct over the art of record during prosecution. Therefore, the petition presents a compelling case of unpatentability based on evidence not previously before the Office.

5. Relief Requested

• Petitioner requests the institution of an inter partes review and the cancellation of claims 1-21 of Patent 7,923,764 as unpatentable.