PTAB

IPR2025-01079

United Microelectronics Corp v. Advanced Integrated Circuit Process LLC

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Semiconductor Device
  • Brief Description: The ’764 patent relates to techniques for improving the driving power and reliability of a metal insulator semiconductor field-effect transistor (MISFET). This is achieved by extending a high-dielectric-constant (high-k) gate insulating film from under the gate electrode to under a sidewall, and by making the high-k film thicker under the gate electrode than it is under the sidewall.

3. Grounds for Unpatentability

Ground 1: Claims 1, 4-5, and 14-19 are obvious over Matsumoto

  • Prior Art Relied Upon: Matsumoto (Application # 2003/0025135).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Matsumoto’s first and fourth embodiments disclose all limitations of the challenged claims. Specifically, Matsumoto teaches a MOSFET with a multilayer sidewall structure and a gate insulating film that extends from under a gate electrode. This film is shown to be a high-k dielectric formed on a substrate's active region. Matsumoto’s figures and fabrication process were asserted to clearly show a first insulating sidewall (film 8) and a second insulating sidewall (film 9 or films 9 and 40) formed on the gate electrode. Critically, the gate insulating film is depicted as continuous from under the gate to under the first sidewall, with a smaller thickness under the sidewall than under the gate. Dependent claims were also argued to be met, with film 8 being an "offset sidewall" (claim 4) and the fourth embodiment disclosing a double-layer (oxide and nitride) second sidewall (claim 14).
    • Motivation to Combine (for §103 grounds): Although based on a single reference, Petitioner argued for obviousness by asserting a person of ordinary skill in the art (POSITA) would be motivated to use a high-k dielectric in Matsumoto’s device to address known issues with scaling silicon dioxide. Petitioner also argued it would have been obvious to combine teachings from Matsumoto’s different embodiments, such as applying the triple-layer sidewall of its sixth embodiment to the fourth embodiment to arrive at the structure of claim 15.

Ground 2: Claims 1, 5, and 16-17 are anticipated by Kajiyama

  • Prior Art Relied Upon: Kajiyama (JP Application # 2003-258241).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner asserted that Kajiyama’s first embodiment FET discloses every element of independent claim 1 and dependent claims 5, 16, and 17. Kajiyama teaches a semiconductor device with a high-k gate insulating film on a substrate, a gate electrode on the film, a first insulating sidewall (e.g., ZrO2), and a second insulating sidewall (e.g., Si3N4) covering the first. The fabrication process in Kajiyama explicitly describes etching the high-k film to reduce its thickness in areas outside the gate electrode. The resulting structure shows the high-k film is continuous under the gate electrode and the first sidewall but is thinner under the sidewall. Furthermore, the fabrication process ensures the high-k film does not extend under the second sidewall, directly teaching the limitation of claim 5. The extended width of the insulating film relative to the gate electrode was asserted to anticipate claims 16-17.

Ground 3: Claims 2-3, 6, and 11 are obvious over Matsumoto in view of Wang

  • Prior Art Relied Upon: Matsumoto (Application # 2003/0025135) and Wang (Application # 2006/0131672).

  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner argued that should Matsumoto be found not to teach certain dependent claim limitations, Wang supplies them. Wang teaches using a "buffer insulating film," preferably a thin silicon oxide layer, between the high-k dielectric and the silicon substrate to improve carrier mobility and device reliability; this combination renders claims 2 and 3 obvious. Wang also discloses using Hf-based oxides (e.g., HfSiON) for the high-k layer, teaching the limitation of claim 6. For claim 11, Wang teaches depositing its HfSiON film to a thickness of 0.5 to 5 nm. Petitioner argued that the claimed thickness of "2 nm or less" falls within Wang’s disclosed range, making the limitation obvious.
    • Motivation to Combine (for §103 grounds): A POSITA would combine Wang’s teachings with Matsumoto's device to solve a known problem. Wang explicitly motivated the use of a buffer layer to mitigate undesirable interactions between high-k dielectrics and the underlying silicon substrate. A POSITA would therefore apply this known technique to improve the performance and reliability of Matsumoto’s similar device.
    • Expectation of Success: A POSITA would have an expectation of success because Wang describes using conventional, established methods for forming the buffer and high-k layers, which would be straightforward to integrate into Matsumoto’s fabrication process.

  • Additional Grounds: Petitioner asserted additional obviousness challenges based on combinations of Matsumoto or Kajiyama with references teaching specific materials (Wilk), sidewall structures (Mutou, Bu), or film characteristics (Sim, Ono).

4. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-6 and 11-19 of the ’764 patent as unpatentable.