PTAB

IPR2025-01082

Taiwan Semiconductor Mfg Co Ltd v. Marlin Semiconductor Ltd

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Three Dimensional Tri-Gate Device with Strained Silicon Channel
  • Brief Description: The ’181 patent discloses a three-dimensional Triple-Gate (Tri-gate) FinFET device. The device features a composite fin structure comprising a silicon germanium (SiGe) core and a strained silicon epitaxy layer grown on the surface of the core, which is intended to provide superior carrier mobility and drive current.

3. Grounds for Unpatentability

Ground 1: Claims 1-10 are anticipated by, or alternatively obvious over, Lee

  • Prior Art Relied Upon: Lee (Patent 7,045,401).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Lee discloses every limitation of the challenged claims. Lee teaches a "strained silicon finFET device" that is explicitly described as a "triple gate" device, satisfying the preamble. The core of the invention, a composite fin structure, was allegedly disclosed in Lee as a SiGe "seed fin" (the core) with a "strained silicon layer" (the epitaxy layer) grown on its surface. Petitioner mapped Lee's "gate 103," source/drain regions, and "gate dielectric 110" to the corresponding limitations for the gate strip, source/drain regions, and gate insulating layer in independent claims 1 and 6. For dependent claims, Petitioner asserted that Lee's figures show a substantially flat top surface and vertical sidewalls (claim 2), that Lee's disclosed dimensional ranges for the fin core and epitaxy layer inherently include embodiments where the fin's width is approximately equal to its height (claim 3), and that Lee explicitly discloses the claimed thickness range for the strained silicon layer (claims 4 and 9) and the use of polysilicon or metal for the gate (claims 5 and 10).
    • Motivation to Combine (for §103 grounds): As an alternative for claim 3, Petitioner argued that Lee's disclosed dimensional ranges for the fin components substantially overlap with dimensions that satisfy the claim. A Person of Ordinary Skill in the Art (POSITA) would have found it obvious to select dimensions within Lee's ranges to achieve an approximately equal height and width, as this was a known design choice for ensuring a fully depleted device, which was a stated goal in Lee. This modification was presented as routine optimization, not an inventive step.
    • Expectation of Success (for §103 grounds): A POSITA would have had a high expectation of success in adjusting the fin dimensions as it involved routine optimization of known parameters using standard fabrication techniques to achieve a well-understood performance goal (full depletion).

Ground 2: Claim 3 is obvious over Lee in view of Chau

  • Prior Art Relied Upon: Lee (Patent 7,045,401) and Chau (Application # 2004/0036126).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner contended that Lee teaches the base Tri-gate device with a composite fin structure, and Chau provides the explicit teaching for modifying its dimensions to have a width approximately equal to its height. Chau is directed to "tri-gate" devices and teaches varying fin height and width to ensure full depletion, a key performance characteristic. Chau's Figure 6 provides a graph showing workable height and width dimensions for achieving a fully depleted transistor, and Petitioner demonstrated how points on this graph correspond to composite fin structures with substantially equal height and width.
    • Motivation to Combine (for §103 grounds): A POSITA would combine Lee's device with Chau's teachings to optimize the device for full depletion and its associated benefits, such as improved short-channel performance. Chau explicitly taught that selecting fin dimensions, including those with equal height and width, was a known method for achieving this goal. Furthermore, using such dimensions was argued to simplify fabrication compared to the high-aspect-ratio fins of earlier devices.
    • Expectation of Success (for §103 grounds): Success was expected because it involved applying known design principles from Chau to a compatible device structure from Lee using well-known fabrication processes to achieve predictable performance improvements.

Ground 3: Claims 1-10 are anticipated by, or alternatively obvious over, Sugiyama

  • Prior Art Relied Upon: Sugiyama (Patent 6,774,390).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Sugiyama's metal-insulator-semiconductor field-effect transistor (MISFET) is a three-dimensional triple-gate device that anticipates all challenged claims. Sugiyama was alleged to disclose a composite fin structure with a "projecting SiGe layer" (core) and a "strained Si layer" (epitaxy layer) formed on the side and upper surfaces. A "band-like gate electrode" wraps three sides of this structure, meeting the gate strip limitation. Petitioner mapped all other elements of independent claims 1 and 6 and their dependent claims, noting that Sugiyama discloses specific dimensional ranges that result in a fin width approximately equal to its height (claim 3), a strained silicon layer thickness of 50-300 Ångstroms (claims 4 and 9), and a polysilicon gate (claims 5 and 10).
  • Additional Grounds: Petitioner asserted additional obviousness challenges, including that claims 1-2 and 4-10 are anticipated by Dakshina (Patent 6,803,631), and that claim 3 is obvious over Sugiyama in view of Chau and over Dakshina in view of Chau. These grounds relied on similar arguments, presenting Dakshina as another primary reference disclosing the fundamental Tri-gate device, and using Chau's teachings as the motivation to modify the fin dimensions to be approximately equal in height and width.

4. Relief Requested

  • Petitioner requests institution of IPR and cancellation of claims 1-10 of the ’181 patent as unpatentable.