PTAB

IPR2025-01082

Taiwan Semiconductor Manufacturing Company Ltd. v. Marlin Semiconductor Limited

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1. Case Identification

2. Patent Overview

  • Title: Three-Dimensional Triple-Gate Device With Strained Silicon Channel
  • Brief Description: The ’181 patent relates to a three-dimensional Tri-gate FinFET device. The device uses a composite fin structure, comprising a silicon germanium (SiGe) core and a strained silicon epitaxy layer, to enhance carrier mobility and provide superior drive current.

3. Grounds for Unpatentability

Ground 1: Claims 1-10 are anticipated or, alternatively, obvious over Lee.

  • Prior Art Relied Upon: Lee (Patent 7,045,401)
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Lee, which discloses a strained silicon FinFET device, teaches every limitation of the challenged claims. Lee’s device includes a composite fin structure (a SiGe “seed fin” covered by an epitaxially grown “strained silicon layer”) and a gate that wraps three sides of the fin channel, qualifying it as a tri-gate device. The portions of Lee's fin not covered by the gate constitute the source/drain regions, and a gate dielectric electrically isolates the gate from the fin. For dependent claims, Petitioner asserted Lee discloses a fin with a substantially flat top and vertical sidewalls (claim 2), a strained epitaxy layer thickness of 50-150 Ångstroms which falls within the claimed 50-300 Ångstrom range (claims 4 and 9), and a gate made of polysilicon or metal (claims 5 and 10).
    • Key Aspects: For claim 3, which requires the fin’s width to be approximately equal to its height, Petitioner argued Lee anticipates this limitation. Lee discloses preferred ranges for the SiGe core’s height (10-200 nm), its width (5-100 nm), and the epitaxy layer’s thickness (5-15 nm). Petitioner demonstrated that selecting dimensions from the endpoints or middle of these disclosed ranges (e.g., 10 nm height, 5 nm width, 5 nm epitaxy thickness) results in a composite fin with an equal height and width of 15 nm. Petitioner contended that because Lee’s disclosed ranges inherently describe a structure with the claimed 1:1 aspect ratio, it anticipates claim 3.

Ground 2: Claims 1-10 are anticipated or, alternatively, obvious over Sugiyama.

  • Prior Art Relied Upon: Sugiyama (Patent 6,774,390)
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner asserted that Sugiyama, which is directed to a metal-insulator-semiconductor field-effect transistor (MISFET), discloses a three-dimensional tri-gate device meeting all limitations. Sugiyama’s device consists of a “projecting SiGe layer” (core) and a “strained Si layer” (epitaxy layer) grown on its side and upper surfaces, forming the claimed composite fin. A “band-like gate electrode” wraps the three surfaces of this fin. Similar to Lee, Sugiyama was argued to teach the flat/vertical fin shape, the required thickness range for the strained silicon layer (disclosing 5-30 nm, which is 50-300 Ångstroms), and the use of polysilicon for the gate electrode.
    • Motivation to Combine (for §103 grounds): The motivation arguments for obviousness were presented as alternatives to anticipation. For claim 3, Petitioner argued that Sugiyama discloses dimensional ranges for the fin core and epitaxy layer which, when combined, result in a height-to-width ratio (e.g., 0.92) a POSITA would consider approximately equal to 1. As no criticality is associated with the exact 1:1 ratio, its selection would have been an obvious design choice.
    • Expectation of Success (for §103 grounds): A POSITA would have had a reasonable expectation of success in achieving the claimed dimensions, as it involved routine optimization of known parameters for a known purpose (improving performance).

Ground 3: Claims 1-2 and 4-10 are anticipated by Dakshina.

  • Prior Art Relied Upon: Dakshina (Patent 6,803,631)

  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner argued Dakshina teaches a FinFET with all elements of the challenged claims except claim 3. Dakshina’s device uses a "fin" made of SiGe (core) with an epitaxially grown "strained layer" of silicon on its surface, creating the composite fin structure. The fin is explicitly formed with a lattice mismatch to induce tensile strain and improve carrier mobility. A gate electrode covers three surfaces of the fin (top and both vertical sides), separated by a gate dielectric. Petitioner mapped Dakshina’s disclosures to the limitations of claims 1-2 and 4-10, noting it teaches the tri-gate structure, the composite fin with lattice mismatch, flat top/vertical sidewalls, a strained layer thickness of 5 nm (50 Ångstroms), and a polysilicon gate.

  • Additional Grounds: Petitioner asserted additional obviousness challenges for claim 3 based on combinations of Lee with Chau (Application # 2004/0036126), Sugiyama with Chau, and Dakshina with Chau. In each case, Petitioner argued that Chau teaches varying fin height and width to achieve a fully depleted transistor and explicitly provides examples and graphical data showing dimensions that result in an approximate 1:1 height-to-width ratio. A POSITA would have been motivated to combine Chau's teachings with the primary references to optimize performance and simplify fabrication, making the specific dimensions of claim 3 obvious.

4. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-10 of the ’181 patent as unpatentable.