PTAB

IPR2025-01302

Taiwan Semiconductor Mfg Co Ltd v. Advanced Integrated Circuit Process LLC

Log In
Key Events
Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Semiconductor Device
  • Brief Description: The ’373 patent relates to a semiconductor device with a complementary metal-insulator-semiconductor (CMIS) dual-gate structure, particularly for devices having both logic and SRAM circuits. The invention modifies this known structure by varying the doping concentrations of the p-type (PMIS) and n-type (NMIS) gate electrodes between the logic and SRAM sections.

3. Grounds for Unpatentability

Ground 1: Obviousness over Tamaki - Claims 1-4, 8-9, and 11-14 are obvious over Tamaki.

  • Prior Art Relied Upon: Tamaki (Application # 2008/0036010).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner asserted that Tamaki teaches a semiconductor device with distinct SRAM and logic sections, each featuring a CMIS dual-gate electrode structure similar to that described in the ’373 patent. Tamaki discloses two embodiments with different impurity concentration relationships for the NMIS and PMIS gate electrodes in the SRAM and logic sections. Petitioner argued that Tamaki’s first embodiment teaches the impurity relationships for claims 1-2, 4, 8-9, and 12-14, where the logic PMIS concentration is greater than the SRAM PMIS, and the logic NMIS is greater than the SRAM NMIS. Petitioner further argued that Tamaki’s second embodiment teaches the relationships for claims 1-4, 8-9, 11, and 14, where the logic NMIS concentration is greater than the SRAM NMIS, while the PMIS concentrations are substantially equal. Both embodiments were alleged to disclose the claimed first and second dual-gate electrodes, their separation, their location on active regions, and their connection over an isolation region.
    • Key Aspects: Petitioner contended that the patent examiner overlooked Tamaki’s explicit teachings during prosecution, particularly its disclosure of a first dual-gate electrode separated from a second dual-gate electrode, which was a key reason for allowance.

Ground 2: Obviousness over Tamaki in view of Sumi - Claims 5 and 7 are obvious over Tamaki in view of Sumi.

  • Prior Art Relied Upon: Tamaki (Application # 2008/0036010) and Sumi (Japanese Patent 9181194).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that while Tamaki teaches most limitations, it does not explicitly disclose the specific impurity concentration relationship required by claims 5 and 7, where a portion of a gate electrode over an active region has a lower concentration than the portion over the adjacent isolation region. Sumi was introduced to supply this teaching. Sumi addresses the known problem of mutual dopant diffusion in dual-gate structures by teaching a high-concentration impurity region at the p-n junction over the isolation region to act as a diffusion barrier. This inherently creates a gate electrode portion over the isolation region with a higher impurity concentration than the portion over the active region.
    • Motivation to Combine: A person of ordinary skill in the art (POSITA) would combine Sumi’s diffusion barrier technique with Tamaki’s device. Tamaki recognized the problem of dopant diffusion but only partially addressed it by lowering overall dopant concentrations. A POSITA would have been motivated to incorporate Sumi’s more effective solution to further suppress diffusion, improve transistor performance, and enable continued device scaling, which was a known industry goal.
    • Expectation of Success: The combination involved standard and well-understood semiconductor fabrication techniques, such as forming high-concentration arsenic-doped regions, which were compatible with Tamaki's process flow. Therefore, a POSITA would have had a reasonable expectation of success.

Ground 3: Obviousness over Igarashi - Claims 1-4, 6, and 8-14 are obvious over Igarashi.

  • Prior Art Relied Upon: Igarashi (Application # 2008/0042218).

  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner asserted that Igarashi teaches a semiconductor memory device having an SRAM memory array and peripheral logic circuits, which together meet the limitations of the challenged claims. Igarashi’s inverter structures, used in both SRAM and logic circuits, employ a shared polysilicon gate for the PMOS and NMOS transistors, which Petitioner mapped to the claimed "dual-gate electrode." Igarashi was argued to teach physically separate first (logic) and second (SRAM) dual-gate electrodes. Critically, Igarashi discloses a fabrication process where the logic PMOS gate receives a higher p-type dopant concentration than the SRAM PMOS gate, while the NMOS gates receive substantially equal n-type doping. This directly meets the impurity concentration limitations of independent claim 1 and several dependent claims. For claim 2, Petitioner argued a POSITA would have understood that logic circuits inherently require wider isolation regions than densely packed SRAM arrays for signal integrity, making the claimed width difference an obvious design choice.
    • Key Aspects: The argument for claim 6 relied on the assertion that Igarashi’s decoupled implantation steps for NMOS gates would have motivated a POSITA to explore varying dopant levels as a matter of routine optimization, including making the logic NMIS concentration lower than the SRAM NMIS.

  • Additional Grounds: Petitioner asserted additional obviousness challenges, including that all claims (1-14) are obvious over Igarashi in view of Sumi, and that claim 2 is obvious over combinations of Igarashi with Tamaki, and Igarashi with Sumi and Tamaki, relying on similar motivations to combine to solve known problems in the art.

4. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-14 of the ’373 patent as unpatentable.