PTAB

IPR2025-01449

SK Hynix Inc v. Advanced Memory Technologies LLC

Log In
Key Events
Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Semiconductor Memory Device
  • Brief Description: The ’888 patent discloses a semiconductor memory device for erasing and writing data. The claimed invention uses a single regulator coupled to first and second switches to supply different voltages to a voltage-applying transistor and a memory cell, respectively, differing from prior art that allegedly used two separate regulators.

3. Grounds for Unpatentability

Ground 1: Claims 1 and 21 are anticipated by Tomita.

  • Prior Art Relied Upon: Tomita (Patent 5,907,505).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Tomita, which discloses a power source circuit for non-volatile semiconductor memory, teaches every element of claims 1 and 21. Petitioner mapped Tomita’s boost circuit (WL/SL C.P. 1) to the claimed "regulator," its switch circuits (PBL S.W. 8 and WL S.W. 6) to the "first and second switches," and its "write transistor 13" to the "voltage applying transistor." For claim 21, Petitioner asserted that Tomita’s second boost circuit (BL C.P. 2), which supplies a high potential to the write transistor, meets the limitation of an output of a booster circuit coupled to the voltage applying transistor.

Ground 2: Claims 1, 3, 5, 20-21 are obvious over Tomita in view of Im.

  • Prior Art Relied Upon: Tomita (Patent 5,907,505) and Im (Patent 8,116,132).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner asserted that the combination of Tomita and Im renders the challenged claims obvious. The primary combination proposes implementing Tomita’s switch circuits (6 and 8), which select between different input potentials, with a plurality of transistor switches as taught by Im's switch unit (120). Im discloses a conventional switch unit with multiple transistor switches for selectively applying different wordline voltages to a memory cell.
    • Motivation to Combine: A POSITA would combine Tomita and Im because both references are in the same field of flash memory power supply design and share the goal of improving memory cell reliability. Tomita teaches improving reliability by providing multiple voltage sources to a switch. Im provides a well-known, transistor-based implementation for such a multi-input switch circuit. Petitioner also argued that market forces demanding higher-capacity multi-level cell (MLC) memory would have motivated a POSITA to look to references like Im for multi-level wordline voltage generation to supplement Tomita's teachings.
    • Expectation of Success: A POSITA would have had a reasonable expectation of success because Im’s switch design was a "conventional method" for selecting word line voltages, and its implementation into Tomita’s architecture would have been a straightforward integration of known components to achieve a predictable result.

Ground 3: Claims 1, 3, 5, and 20-21 are anticipated by Nakayama.

  • Prior Art Relied Upon: Nakayama (an Aug. 1989 IEEE Journal article).

  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner contended that Nakayama, which describes a 256K EEPROM, discloses all limitations of the challenged claims. Petitioner mapped Nakayama’s "high-voltage generator" to the claimed "regulator." Transistors within Nakayama's column latch (T1) and high-voltage generator were mapped to the claimed "first," "second," and "fourth" switches. Another transistor in the column latch was identified as the "voltage applying transistor." Petitioner argued that Nakayama discloses distinct "program" and "erase" operation modes that satisfy the operational mode limitations of claim 5. For claim 21, Nakayama's charge pump circuit was mapped to the claimed "booster circuit."

  • Additional Grounds: Petitioner asserted an additional obviousness challenge against claims 1, 3, 5, and 21 based on Tomita in view of Nam (Patent 7,372,747), which relied on a similar theory of implementing Tomita’s switches with the conventional transistor-based switching unit disclosed in Nam.

4. Key Claim Construction Positions

  • Term: "allowing the output voltage of the regulator to be applied to the drain terminal of the memory cell" (from claim 5).
  • Petitioner's Position: Petitioner argued this phrase is an obvious drafting error and should be construed to mean "allowing the output voltage of the regulator to be applied to the gate of the voltage applying transistor." The rationale is that claim 1, from which claim 5 depends, recites coupling the regulator’s output to the gate of the voltage applying transistor. Further, the ’888 patent’s specification consistently describes the regulator's output being supplied to the gate of the voltage applying transistor to control the voltage applied to the memory cell, not being directly applied to the memory cell’s drain.

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1, 3, 5, 20, and 21 of Patent 8,593,888 as unpatentable.