PTAB

IPR2025-01532

Apple Inc v. Redstone Logics LLC

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petition

1. Case Identification

2. Patent Overview

  • Title: Power Management for a Multi-Core Processor
  • Brief Description: The ’339 patent relates to a system for power management in a multi-core processor by grouping processor cores into distinct sets that can be operated with independent, dynamically adjusted supply voltages and clock signals generated by separate phase-locked loops (PLLs).

3. Grounds for Unpatentability

Ground 1: Claims 1-3, 5, 8, 10-11, 14, and 21 are obvious over White in view of Talwar and Lee.

  • Prior Art Relied Upon: White (Patent 7,263,457), Talwar (Application # 2009/0271646), and Lee (a 2007 IEEE conference paper).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that White disclosed a multi-core processor where each logic core could operate at independent voltages and frequencies, controlled by power management logic and supplied by voltage and frequency regulators. White’s frequency regulators included PLLs, and a "common bridge logic" provided an interface for communication between cores. Petitioner asserted that White’s per-core approach was inefficient for a large number of cores. Talwar taught grouping cores into "clusters," where all cores in a cluster share a single voltage source and frequency, improving efficiency over per-core Dynamic Voltage and Frequency Scaling (DVFS). Lee disclosed a DVFS scheme for multiple independent power "domains," each with its own supply voltage and PLL-generated clock. Critically, Lee taught using an interface with level shifters and synchronizers for communication between domains operating at different voltages and frequencies. The proposed combination results in a multi-core processor with two sets (clusters) of cores, each with an independent voltage and PLL-driven clock signal, and an interface block for communication, as claimed.
    • Motivation to Combine: A Person of Ordinary Skill in the Art (POSITA) would combine Talwar's efficient core clustering method with White's foundational multi-core DVFS system to better manage processors with many cores while conserving chip space. A POSITA would then look to Lee to provide known, specific implementation details for the combined system, such as how to generate independent clocks for each cluster using separate PLLs, how to implement the required communication interface using level shifters and synchronizers, and how to arrange the clusters in rows on the chip.
    • Expectation of Success: A POSITA would have a reasonable expectation of success in making the combination due to the use of common, well-understood components and the advanced state of the art at the time.

Ground 2: Claims 1-3, 5, 8, 10-11, 14, and 21 are obvious over Elgebaly in view of Lee.

  • Prior Art Relied Upon: Elgebaly (Application # 2007/0096775) and Lee.
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Elgebaly taught adaptive voltage scaling in a multi-core processor where multiple cores could share a common clock and/or a common supply voltage. Elgebaly explicitly disclosed that its clock generator may include one or more PLLs to generate the clock signals. This combination provided the claimed "first" and "second" sets of processor cores, each configured to receive a dynamically adjusted supply voltage and a PLL-generated clock signal. While Elgebaly taught this grouping, it lacked specific details on how to manage communication between groups operating at different voltages or frequencies. Lee supplied these missing details by teaching domain converters with level shifters and synchronizers.
    • Motivation to Combine: A POSITA implementing Elgebaly's system of grouped cores would naturally turn to a reference like Lee to find a known solution for the predictable problem of communicating between domains with different power and clock characteristics. Lee provided the necessary, well-known circuits (level shifters, synchronizers) and layout strategies (arranging domains in rows) to complete the system described by Elgebaly.
    • Expectation of Success: The combination involved applying known techniques from Lee to solve a known problem in the system of Elgebaly, using standard components with predictable results.

Ground 3: Claim 9 is obvious over Elgebaly and Lee in view of Vajda.

  • Prior Art Relied Upon: Elgebaly, Lee, and Vajda (Application # 2012/0060170).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground built upon the combination of Elgebaly and Lee from Ground 2, which established a multi-core processor with separate regions for different sets of cores. Claim 9 specifically requires that the first and second regions are "overlapping." Vajda taught a chip layout designed to mitigate thermal "hot spots" by arranging higher-frequency cores in a checkerboard pattern, surrounded by lower-frequency cores. Petitioner argued this checkerboard arrangement inherently created overlapping regions containing the first set of cores (e.g., higher-frequency) and the second set of cores (e.g., lower-frequency).
    • Motivation to Combine: A POSITA designing the Elgebaly/Lee system would be aware of the common problem of thermal management in multi-core processors. If overheating were a concern with Lee's row-based layout, the POSITA would be motivated to adopt Vajda's checkerboard layout as a known, alternative solution to mitigate hot spots. This represented an obvious design choice between known layout strategies to address a well-understood design constraint.
    • Expectation of Success: A POSITA would expect success as it involved substituting one known layout for another to achieve the predictable benefit of improved thermal performance.

4. Relief Requested

  • Petitioner requests institution of IPR and cancellation of claims 1-3, 5, 8-11, 14, and 21 of the ’339 patent as unpatentable.