PTAB

IPR2025-01532

Apple Inc v. Redstone Logics LLC

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1. Case Identification

2. Patent Overview

  • Title: Power Management for a Multi-Core Processor
  • Brief Description: The ’339 patent discloses power management techniques for a multi-core processor. The system reduces power consumption by using dynamic supply voltage and clock speed control, which can be applied separately to different groups, or "sets," of processor cores.

3. Grounds for Unpatentability

Ground 1: Obviousness over White, Talwar, and Lee - Claims 1-3, 5, 8, 10-11, 14, and 21 are obvious over White in view of Talwar and Lee.

  • Prior Art Relied Upon: White (Patent 7,263,457), Talwar (Application # 2009/0271646), and Lee (a 2007 IEEE conference paper).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that White disclosed a multi-core processor where each core can be configured to operate at independent voltages and frequencies using dynamic voltage and frequency scaling (DVFS). Talwar taught grouping cores into "clusters" to receive power from a single voltage source while allowing each cluster to have a different frequency, a known method to efficiently scale DVFS to processors with many cores. Lee provided the necessary implementation details for such a multi-domain system, including the use of phase-locked loops (PLLs) to generate independent clock signals for each domain, and an interface block with level shifters and synchronizers to facilitate communication between domains operating at different voltages and clock rates.
    • Motivation to Combine: A person of ordinary skill in the art (POSITA) would combine White and Talwar to apply DVFS to a processor with many cores, using Talwar's clustering to overcome the practical chip space constraints of White's per-core approach. A POSITA would then look to Lee for well-known implementation details on clock generation, inter-domain communication, and physical layout (e.g., in rows or "stripes") to realize the benefits of the combined White/Talwar system.
    • Expectation of Success: A POSITA would have had a reasonable expectation of success in making the combination due to the specific implementation details provided by the references and the use of common, well-understood components and circuit designs.

Ground 2: Obviousness over Elgebaly and Lee - Claims 1-3, 5, 8, 10-11, 14, and 21 are obvious over Elgebaly in view of Lee.

  • Prior Art Relied Upon: Elgebaly (Application # 2007/0096775) and Lee (a 2007 IEEE conference paper).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner asserted that Elgebaly taught a multi-core system with "highly efficient adaptive voltage scaling," where multiple processing cores may share a common clock and supply voltage that are jointly set. Elgebaly's clock generator explicitly used one or more PLLs to generate the clocks. This combination disclosed the claimed "first set" and "second set" of processor cores, each receiving an independent, dynamically adjusted supply voltage and a clock signal from a PLL. Lee was relied upon to provide further details, such as its "Domain Converter" which functions as the claimed interface block, containing the necessary level shifters and synchronizers for communication between the different power domains taught by Elgebaly.
    • Motivation to Combine: A POSITA implementing Elgebaly's system would be motivated to consult a reference like Lee to fill in implementation details. While Elgebaly taught independent or grouped DVFS, it lacked specifics on the circuitry required for communication between cores operating at different voltages or frequencies. Lee directly addressed this by teaching a Domain Converter with level shifters and synchronizers, making it a natural and necessary addition to complete Elgebaly's system.
    • Expectation of Success: Success was expected because the combination involved applying Lee's specific solutions for inter-domain communication to the system architecture disclosed by Elgebaly, using standard components and known design principles.

Ground 3: Obviousness over Elgebaly, Lee, and Vajda - Claim 9 is obvious over Elgebaly and Lee in view of Vajda.

  • Prior Art Relied Upon: Elgebaly (Application # 2007/0096775), Lee (a 2007 IEEE conference paper), and Vajda (Application # 2012/0060170).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground specifically targeted claim 9, which depends from claim 8 and requires that the "first region and the second region are overlapping regions." The primary combination of Elgebaly and Lee taught arranging core domains in separate, non-overlapping rows or "stripes." Petitioner argued that Vajda taught an alternative layout for multi-core chips, arranging higher-frequency and lower-frequency cores in a checkerboard pattern to avoid thermal "hot spots." This checkerboard arrangement inherently results in the claimed "overlapping regions" for different sets of cores.
    • Motivation to Combine: A POSITA designing a multi-core processor based on Elgebaly and Lee would be aware of thermal management as a critical design constraint. Overheating was a well-known problem. Vajda presented a known, viable layout alternative to Lee's stripes specifically to address this issue. Therefore, a POSITA would find it obvious to apply Vajda's checkerboard layout to the Elgebaly/Lee system to improve thermal performance, viewing it as a known design trade-off.
    • Expectation of Success: A POSITA would have expected success as this modification involved selecting between known, alternative chip layout strategies to address a common design problem.

4. Relief Requested

  • Petitioner requested the institution of an inter partes review and cancellation of claims 1-3, 5, 8-11, 14, and 21 of the ’339 patent as unpatentable.