PTAB

IPR2018-01661

InTel Corp v. VLSI Technology LLC

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1. Case Identification

2. Patent Overview

  • Title: Power Reduction Method and Device
  • Brief Description: The ’014 patent discloses a method and device for reducing power consumption in an integrated circuit component, such as a cache memory. The core inventive concept involves determining whether to power down a portion of the component by comparing an estimated power gain against an estimated power loss that would result from the power-down action.

3. Grounds for Unpatentability

Ground I: Obviousness over Takahashi - Claims 1-3 are obvious over Takahashi

  • Prior Art Relied Upon: Takahashi (Patent 5,761,715).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that independent claim 1, which recites determining whether to power down a component based on a relationship between an estimated power gain and an estimated power loss, was rendered obvious by Takahashi. Takahashi was asserted to teach a power management system for a cache memory that determines whether to power down a cache way (a portion of the component) during a low-power mode. This determination is based on comparing the cache-miss rate (a proxy for power loss, as misses increase dynamic power consumption) against a predetermined threshold value (a proxy for power gain). Petitioner contended this comparison of proxy values met the "relationship" limitation of claim 1. Dependent claims 2 and 3 were argued to be obvious as Takahashi explicitly discloses the component is a cache memory with independently powered portions (cache ways).
    • Motivation to Combine (for §103 grounds): Not applicable (single reference ground).
    • Expectation of Success (for §103 grounds): Not applicable (single reference ground).

Ground II: Obviousness over Takahashi and Hu - Claims 1-5, 15, and 16 are obvious over Takahashi in view of Hu

  • Prior Art Relied Upon: Takahashi (Patent 5,761,715) and Hu (an ACM article titled "Let Caches Decay").
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner asserted that while Takahashi taught using proxies (cache-miss rate and a threshold) for the claimed power loss/gain comparison, Hu explicitly taught the very concept claimed: measuring the actual static power saved (power gain) from turning off cache lines and comparing it to the extra dynamic power dissipated (power loss) from induced cache misses and writebacks. The combination was argued to render claim 1 obvious. For dependent claims 4, 5, 15, and 16, which recite the determination being responsive to "dirty" information, Petitioner argued Hu taught this as well. Hu's power loss calculation explicitly considered the additional dynamic power consumed by writebacks, which occur when powering down a cache line containing dirty information (information modified but not yet written to main memory).
    • Motivation to Combine (for §103 grounds): A POSITA would combine Takahashi and Hu because both addressed the identical problem of reducing power consumption in cache memory. Petitioner argued that implementing Hu’s explicit power gain/loss calculation method would have been a routine and predictable modification to improve Takahashi’s proxy-based system. Hu's quantitative analysis provided a more refined way to achieve Takahashi's stated goal of reliably reducing power consumption.
    • Expectation of Success (for §103 grounds): A POSITA would have a reasonable expectation of success because applying Hu's more precise power measurement techniques to Takahashi's power-gating framework was a straightforward combination of known elements to achieve a predictable result.

Ground III: Obviousness over Takahashi, Hu, and Cohen - Claims 4, 5, 15, and 16 are obvious over Takahashi, Hu, and Cohen

  • Prior Art Relied Upon: Takahashi (Patent 5,761,715), Hu (ACM article), and Cohen (Patent 7,127,560).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground built upon Ground II to further strengthen the obviousness argument for the claims dependent on "dirty" information (claims 4, 5, 15, and 16). While Hu taught considering the power cost of writebacks for dirty lines, Cohen was added for its explicit disclosure of mechanisms for handling dirty data. Cohen taught using "dirty bits" to track such data and disclosed a "busy bit counter" to count the number of dirty bits in a portion of a cache. Petitioner argued this directly corresponded to the '014 patent's method of counting dirty lines to estimate power loss.
    • Motivation to Combine (for §103 grounds): A POSITA, seeking to implement the power loss calculations taught by Hu, would have been motivated to consult Cohen to understand the specific mechanisms and costs associated with handling dirty cache lines. Cohen provided concrete implementation details (like dirty bit counters) for the abstract concept of "additional writebacks" in Hu. Combining the three references was presented as a logical path to achieve the common goal of efficient power management that accounts for the status of data within the cache.
    • Expectation of Success (for §103 grounds): A POSITA would have expected success in combining the references, as Cohen provided a well-understood method for implementing the very cost-analysis (related to dirty data) that Hu suggested was necessary for an effective power-saving policy within the framework Takahashi provided.

4. Relief Requested

  • Petitioner requested institution of an inter partes review and cancellation of claims 1-5, 15, and 16 of Patent 8,020,014 as unpatentable.