Intel Corp v. VLSI Technology LLC

1. Case Identification

• Case #: IPR2018-01661
• Patent #: 8,020,014
• Filed: September 7, 2018
• Petitioner(s): Intel Corporation
• Patent Owner(s): VLSI Technology LLC
• Challenged Claims: 1-5, 15, and 16

2. Patent Overview

• Title: Method for Power Management and Device Having Power Management Capabilities
• Brief Description: The ’014 patent discloses a power reduction method and device, particularly for cache memory in an integrated circuit. The core concept involves determining whether to power down a portion of a component by comparing an estimated power gain against an estimated power loss that would result from the power-down action.

3. Grounds for Unpatentability

Ground I: Obviousness over Takahashi - Claims 1-3 are obvious over Takahashi.

• Prior Art Relied Upon: Takahashi (Patent 5,761,715).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Takahashi taught all limitations of claims 1-3. Takahashi disclosed a power reduction method for cache memory that involved selectively deactivating portions of the cache (cache ways) during a "low power consumption mode." To meet the key limitation of claim 1—determining whether to power down based on a relationship between estimated power gain and loss—Petitioner asserted that Takahashi taught comparing a measured cache-miss rate against a predetermined value. The cache-miss rate served as a proxy for estimated power loss (as higher misses increase power consumption), and the predetermined value served as a proxy for estimated power gain. If the miss rate did not exceed this value, a cache way was powered down.
  • Motivation to Combine (for §103 grounds): Not applicable (single reference ground).
  • Expectation of Success (for §103 grounds): Not applicable.

Ground II: Obviousness over Takahashi and Hu - Claims 1-5, 15, and 16 are obvious over Takahashi in view of Hu.

• Prior Art Relied Upon: Takahashi (Patent 5,761,715) and Hu (a 2002 ACM journal article titled “Let Caches Decay...”).
• Core Argument for this Ground:
  • Prior Art Mapping: This combination was argued to render the claimed invention obvious by making the power trade-off analysis explicit. While Takahashi used proxies, Hu expressly taught measuring the static power saved (power gain) from turning off cache lines and comparing it to the extra dynamic power dissipated (power loss) from resulting cache misses. Hu’s L2Access:leak ratio quantified this relationship. For claims 4, 5, 15, and 16, which require the determination to be responsive to "dirty" information, Petitioner argued Hu met these limitations. Hu taught that powering down a dirty cache line incurs additional power loss due to the need for a writeback operation and explicitly included the energy cost of an "additional miss (or writeback)" in its power loss calculation. A POSITA would understand that dirty information is tracked using "dirty bits," making Hu's analysis inherently responsive to the amount of information associated with them.
  • Motivation to Combine: A POSITA would combine these references because both addressed the same problem of reducing cache power consumption. A POSITA seeking to improve Takahashi’s proxy-based system would have looked to a reference like Hu, which provided a more precise, quantitative method for evaluating the same power trade-offs. Implementing Hu’s explicit power gain/loss calculation into Takahashi’s framework would have been a routine modification to create a more efficient power management system.
  • Expectation of Success: A POSITA would have an expectation of success because combining Hu’s analytical method with Takahashi’s cache control system involved applying known principles to achieve the predictable result of more efficient power savings.

Ground III: Obviousness over Takahashi, Hu, and Cohen - Claims 4, 5, 15, and 16 are obvious over Takahashi and Hu in view of Cohen.

• Prior Art Relied Upon: Takahashi (Patent 5,761,715), Hu (2002 ACM journal article), and Cohen (Patent 7,127,560).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground strengthened the obviousness arguments for the claims related to "dirty" information by adding Cohen. While Hu taught the principle of accounting for extra power loss from dirty line writebacks, Cohen provided concrete implementation details. Cohen confirmed that "dirty data" is data not stored elsewhere and described specific writeback policies (e.g., "Force-Flush") required before powering down a cache portion. Critically, Cohen disclosed a "busy bit counter" that counts the number of dirty bits in a cache portion to track how much dirty information is present. Petitioner argued this directly corresponded to the dirty bit counter in the ’014 patent and provided a clear mechanism for making the power-down determination responsive to the amount of dirty information.
  • Motivation to Combine: A POSITA implementing the power-saving concept from Takahashi and Hu would be motivated to consult a reference like Cohen for practical guidance on managing dirty data. Cohen provided specific, known techniques, such as using a dirty bit counter, for the very purpose of handling the dirty data writebacks that Hu identified as a critical factor in the power loss calculation. This combination represented the application of a known implementation technique (from Cohen) to improve the existing system (Takahashi and Hu).
  • Expectation of Success: A POSITA would expect success in combining the references because Cohen provided a well-understood solution (a dirty bit counter) for a known sub-problem (tracking dirty data) within the broader framework taught by Takahashi and Hu, leading to the predictable outcome of a more robust power management system.

4. Relief Requested

• Petitioner requested the institution of an inter partes review and the cancellation of claims 1-5, 15, and 16 of the ’014 patent as unpatentable.