DCT

2:25-cv-00171

Longitude Licensing Ltd v. Lenovo Group Ltd

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 2:25-cv-00171, E.D. Tex., 02/13/2025
  • Venue Allegations: Plaintiffs allege venue is proper in the Eastern District of Texas because Defendants conduct business in the district, place infringing products into the stream of commerce with the expectation of sale in the district (including at specific retail locations), and, as foreign entities, may be sued in any judicial district where they are subject to personal jurisdiction.
  • Core Dispute: Plaintiffs allege that semiconductor devices manufactured by Taiwan Semiconductor Manufacturing Company (TSMC) and incorporated into consumer electronics sold by Lenovo, Motorola, and OnePlus infringe five U.S. patents related to advanced semiconductor transistor structures and fabrication methods.
  • Technical Context: The lawsuit concerns foundational technologies for manufacturing modern high-performance integrated circuits, such as FinFETs and strained silicon techniques, which are critical for processors used in smartphones, laptops, and other advanced electronics.
  • Key Procedural History: The complaint alleges that Plaintiffs engaged in extensive pre-suit licensing negotiations with Defendant TSMC beginning in March 2023, which included sending notice letters identifying specific patents and holding multiple meetings. Plaintiffs allege that during these discussions, TSMC acknowledged awareness of the patents and claimed to have prepared draft inter partes review (IPR) petitions, which may be significant for the allegations of willful infringement.

Case Timeline

Date Event
2007-08-09 U.S. Patent No. 7,745,847 Priority Date
2010-06-29 U.S. Patent No. 7,745,847 Issue Date
2010-07-15 U.S. Patent No. 9,093,473 Priority Date
2012-02-09 U.S. Patent No. 9,184,292 Priority Date
2013-05-02 U.S. Patent No. 9,147,747 Priority Date
2015-07-28 U.S. Patent No. 9,093,473 Issue Date
2015-09-29 U.S. Patent No. 9,147,747 Issue Date
2015-11-10 U.S. Patent No. 9,184,292 Issue Date
2017-06-29 U.S. Patent No. 9,953,880 Priority Date
2018-04-24 U.S. Patent No. 9,953,880 Issue Date
2023-03-08 Plaintiffs allegedly sent first pre-suit notice letter
2023-10-31 Plaintiffs and TSMC's customer allegedly held virtual meeting
2023-12-07 Plaintiffs allegedly sent second pre-suit notice letter
2024-05-21 Plaintiffs and TSMC allegedly met in Hsinchu, Taiwan
2025-02-13 Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,745,847 - “Metal Oxide Semiconductor Transistor,” issued June 29, 2010

The Invention Explained

  • Problem Addressed: The patent seeks to address the ongoing challenge of increasing carrier mobility (and thus transistor speed) in ever-shrinking semiconductor devices. Conventional methods for creating mechanical stress in the transistor channel to boost mobility were reaching their limits. (’847 Patent, col. 1:21-48).
  • The Patented Solution: The invention describes a transistor structure where recesses are etched into the substrate next to the gate before spacers are formed. These recesses are then filled with an epitaxial material (e.g., silicon germanium) to create "raised" source and drain regions. This sequence allows for a unique geometry where the spacer sits partially on top of the raised epitaxial layer, a configuration intended to enhance the desired channel strain. (’847 Patent, Abstract; col. 2:21-29).
  • Technical Importance: This "epitaxy-before-spacer" approach represented a method for engineering higher levels of strain in the transistor channel, a critical technique for continuing performance improvements in advanced logic technology. (’847 Patent, col.1:49-52).

Key Claims at a Glance

  • The complaint asserts independent claim 1. (Compl. ¶108).
  • Essential elements of claim 1 include:
    • a gate formed on a semiconductor substrate;
    • two raised epitaxial layers positioned in the substrate next to the gate and above the substrate surface;
    • a spacer on the gate sidewall that extends laterally over a portion of the raised epitaxial layers, where the bottom of the spacer is above the semiconductor substrate surface; and
    • two doped regions next to the sides of the gate.
  • The complaint alleges infringement of "one or more claims," reserving the right to assert others. (Compl. ¶108).

U.S. Patent No. 9,093,473 - “Method for Fabricating Metal-Oxide Semiconductor Transistor,” issued July 28, 2015

The Invention Explained

  • Problem Addressed: The patent addresses manufacturing problems when creating a "polysilicon slot," a process used to cut a single gate structure into two separate gates. The patent notes that if the slot-etching process is poorly controlled, it can leave behind conductive residue or, conversely, over-etch and damage the underlying hard mask and spacers. (’473 Patent, col. 1:42-57).
  • The Patented Solution: The patented method reorders the fabrication steps. It teaches forming a gate pattern, then forming an epitaxial layer in the substrate adjacent to the gate pattern, and only after the epitaxial layer is in place, performing a second etching process to create the slot that divides the gate. This sequence isolates the critical slot-etching step from other sensitive structures. (’473 Patent, Abstract; col. 2:1-10).
  • Technical Importance: This method provides a more robust manufacturing process for creating isolated gate structures, important for components like SRAM cells, while integrating strained silicon techniques, thereby potentially improving manufacturing yield. (’473 Patent, col. 5:1-12).

Key Claims at a Glance

  • The complaint asserts independent claim 1. (Compl. ¶119).
  • Essential elements of claim 1 (a method claim) include:
    • providing a semiconductor substrate;
    • forming a silicon layer and performing a first photo-etching process to create a gate pattern;
    • forming an epitaxial layer adjacent to the sides of the gate pattern; and
    • after forming the epitaxial layer, performing a second photo-etching process to form a slot that physically separates the gate pattern into two gates.
  • The complaint alleges infringement of "one or more claims," reserving the right to assert others. (Compl. ¶119).

U.S. Patent No. 9,184,292 - “Semiconductor Structure with Different Fins of FinFETs,” issued November 10, 2015

  • Technology Synopsis: The patent describes a FinFET structure containing two distinct types of fins on a single substrate. "Odd fins" are formed from the substrate material itself, while "even fins" are formed between them using a different process (e.g., epitaxy) and can differ in material or width. This allows for the integration of different types of transistors on the same chip. (’292 Patent, Abstract; Compl. ¶131).
  • Asserted Claims: Independent claims 1, 9, and 15 are asserted. (Compl. ¶131).
  • Accused Features: The complaint accuses the FinFET structures within semiconductor devices manufactured by TSMC at its 16nm to 3nm process nodes, including those in the Qualcomm Snapdragon X Elite and Snapdragon 8 Gen 3 processors. (Compl. ¶¶ 129, 132).

U.S. Patent No. 9,147,747 - “Semiconductor Structure with Hard Mask Disposed on the Gate Structure,” issued September 29, 2015

  • Technology Synopsis: The patent aims to simplify the formation of electrical contacts in dense integrated circuits. It describes a structure with a hard mask on the metal gate, where the top of the hard mask is level with the surrounding dielectric. This configuration enables a process where contacts to the source/drain regions and contacts to the gate can be created simultaneously, reducing manufacturing complexity and cost. (’747 Patent, Abstract; Compl. ¶142).
  • Asserted Claims: Independent claim 1 is asserted. (Compl. ¶142).
  • Accused Features: The complaint accuses semiconductor devices made using TSMC's 3nm process node, specifically identifying the Qualcomm Snapdragon 8 Elite processor incorporated in the OnePlus 13 smartphone. (Compl. ¶¶ 140, 143).

U.S. Patent No. 9,953,880 - “Semiconductor Device and Method for Fabricating the Same,” issued April 24, 2018

  • Technology Synopsis: The patent describes a method for fabricating a Single Diffusion Break (SDB), an isolation structure in FinFETs. The method involves forming a trench by removing parts of the gate layer, the fin structure, and the shallow trench isolation (STI), and then filling this trench with a dielectric material to form the SDB. This process is designed to improve the integration of SDBs with modern metal gate fabrication flows. (’880 Patent, Abstract; Compl. ¶153).
  • Asserted Claims: Independent claim 1 is asserted. (Compl. ¶153).
  • Accused Features: The complaint accuses the fabrication methods for devices made using TSMC's 3nm process node, specifically identifying the Qualcomm Snapdragon 8 Elite processor incorporated in the OnePlus 13 smartphone. (Compl. ¶¶ 151, 154).

III. The Accused Instrumentality

Product Identification

  • The core accused instrumentalities are semiconductor devices, integrated circuits, and processors fabricated by Defendant TSMC using its 16nm and smaller process nodes (e.g., 16nm, 12nm, 7nm, 6nm, 5nm, 4nm, and 3nm). (Compl. ¶¶ 61, 94). These devices are allegedly incorporated into end-products sold by Defendants Lenovo and OnePlus, such as the Lenovo Yoga Slim 7X laptop, Moto G Play smartphone, and the OnePlus 13, 13R, and Nord N30 5G smartphones. (Compl. ¶¶ 24, 34).

Functionality and Market Context

  • The accused devices are high-performance system-on-chips (SoCs) and processors that serve as the central computing components for modern consumer electronics. The complaint alleges that these chips, such as the Qualcomm Snapdragon series, are manufactured using TSMC’s most advanced fabrication processes, which are essential to their performance and commercial success. (Compl. ¶¶ 24, 110). An annotated micrograph from a technical analysis firm is provided to show the structure of a representative TSMC 5nm semiconductor die. (Compl. ¶112, p. 38).

IV. Analysis of Infringement Allegations

’847 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
a gate formed on a semiconductor substrate The accused devices contain a "Gate" structure formed on a semiconductor fin, as shown in a provided micrograph of a TSMC 5nm process node die. ¶¶109, 112 col. 2:21-22
two raised epitaxial layers positioned respectively in the semiconductor substrate next to the relative sides of the gate and above the surface of the semiconductor substrate The accused devices allegedly have "SiGe epi" regions (raised epitaxial layers) formed in the substrate next to the gate, with a height above the original substrate surface. ¶¶109, 112 col. 2:23-25
a spacer formed on the sidewall of the gate and extending laterally upon a portion of the raised epitaxial layers, and a contact surface...is above the surface of the semiconductor substrate A structure labeled "Spacer" is shown on the gate sidewall. The complaint provides visuals suggesting the spacer's bottom is above the substrate surface due to the raised nature of the adjacent epitaxial layer, thereby meeting the geometric requirements of the claim. ¶¶109, 112 col. 2:25-29
two doped region formed respectively in the semiconductor substrate next to the relative sides of the gate The raised epitaxial layers, which are inherently doped, function as the source/drain regions and are positioned next to the gate, thereby constituting the claimed doped regions. ¶109 col. 2:27-29

Identified Points of Contention

  • Scope Question: A central issue may be the construction of "above the surface of the semiconductor substrate." In a modern FinFET, the "surface" is a complex 3D topography. The parties may dispute whether the accused structure's geometry, particularly the interface between the spacer bottom and the epitaxial layer, meets this limitation as it was understood in the context of the patent.
  • Technical Question: The claim requires the spacer to extend "laterally upon a portion of the raised epitaxial layers." The provided cross-sectional micrograph from the complaint shows a "Spacer" and "SiGe epi" on a TSMC 5nm die (Compl. ¶112, p. 38). A factual question will be whether this two-dimensional view is sufficient to establish the specific three-dimensional overlap required by the claim language.

’473 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
providing a semiconductor substrate; forming a silicon layer...; performing a first photo-etching process...for forming a gate pattern The accused manufacturing process allegedly begins by forming an initial "gate pattern" (a dummy gate) on a semiconductor substrate. A provided micrograph shows structures labeled "dummy gate" as evidence of this step. ¶¶120, 123 col. 6:39-42
forming an epitaxial layer in the semiconductor substrate adjacent to two sides of the gate pattern After the gate pattern is formed, epitaxial source/drain regions are allegedly grown in the substrate adjacent to the sides of the pattern. ¶120 col. 6:42-44
after forming the epitaxial layer, performing a second photo-etching process...to form a slot...to physically separate the gate pattern into two gates The complaint alleges that after the epitaxial source/drains are formed, a "slot" is etched to cut the continuous dummy gate structure. A micrograph from an analysis of a TSMC 7nm process die is used to illustrate this "Slot." (Compl. ¶123, p. 42). ¶¶120, 123 col. 6:44-49

Identified Points of Contention

  • Scope Question: Does the term "gate pattern" as used in the patent, which has a 2010 priority date, read on the "dummy gate" used in the accused modern replacement-metal-gate (RMG) process? Defendants may argue a dummy gate is a temporary placeholder, not the final "gate" contemplated by the patent.
  • Evidentiary Question: Infringement of this method claim depends on the specific sequence of manufacturing steps. A key factual dispute will be what evidence Plaintiffs can produce, beyond static images of a finished product, to prove that TSMC’s proprietary process performs the slot-cutting etch after the epitaxial growth step, as required by the claim.

V. Key Claim Terms for Construction

For the ’847 Patent

  • The Term: "raised epitaxial layers"
  • Context and Importance: This term is the core of the invention's structure. The relationship between the "raised" nature of these layers and the overlying spacer is a critical limitation (claim 1), so its definition will be central to determining infringement. Practitioners may focus on this term because the degree to which a layer must be "raised" to meet the claim is not explicitly quantified.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The specification describes the process as forming "epitaxial layers 220 in the recesses 218" (’847 Patent, col. 3:34-36). This could support an interpretation that any epitaxially grown source/drain region formed in a recess qualifies, without a strict height requirement.
    • Evidence for a Narrower Interpretation: The specification states the layer "may be grown higher than the surface of the semiconductor substrate 200, so as to form a raised epitaxial layer 220" (’847 Patent, col. 3:37-39). A defendant could argue this language, combined with figures like Fig. 5 showing a distinct elevation, requires the layer to protrude above the main substrate plane by a meaningful amount.

For the ’473 Patent

  • The Term: "gate pattern"
  • Context and Importance: The claim requires a specific sequence: forming a "gate pattern," then an epitaxial layer, then cutting a slot in the "gate pattern." The accused devices are alleged to be made with a dummy gate process. Whether this sacrificial "dummy gate" constitutes a "gate pattern" under the patent is determinative for infringement.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The patent describes forming the gate pattern from a "polysilicon layer" (’473 Patent, col. 6:45-51), which is the same material often used for dummy gates. Plaintiffs may argue that any sacrificial structure that defines the ultimate gate location serves as the "gate pattern" for the purposes of the claimed method.
    • Evidence for a Narrower Interpretation: The patent repeatedly refers to fabricating a "gate of the transistor" (’473 Patent, col. 1:30-34). A defendant may argue this ties the term "gate pattern" to the final, electrically functional gate, not a temporary, sacrificial structure that is later removed and replaced in an RMG process.

VI. Other Allegations

Indirect Infringement

  • The complaint alleges both induced and contributory infringement against all Defendants. The inducement allegations against TSMC are based on it allegedly providing customers with infringing chips, design kits, and technical instructions that enable and encourage the creation of infringing end-products (Compl. ¶¶ 99-101). The inducement claims against Lenovo and OnePlus are based on their encouraging the use and sale of products containing the infringing chips (Compl. ¶¶ 59, 70). Contributory infringement is based on the allegation that the accused chips are a material component of the inventions and have no substantial non-infringing uses (Compl. ¶¶ 60, 93).

Willful Infringement

  • Willfulness is alleged against all Defendants. The allegations against TSMC are based on alleged pre-suit knowledge dating to at least October 2023, citing specific notice letters and meetings where the patents-in-suit were discussed and TSMC allegedly showed it had prepared draft IPR petitions (Compl. ¶¶ 82-85, 103). For Lenovo and OnePlus, the allegations are based on knowledge of the patents occurring "at least as early as the filing of the present Complaint" (Compl. ¶¶ 66, 78).

VII. Analyst’s Conclusion: Key Questions for the Case

  • A core legal issue will be one of technological translation: can claim terms from patents with 2007-2012 priority dates, such as "gate pattern" and "raised epitaxial layers," be construed to read on the structures and processes of modern FinFETs made with replacement-metal-gate flows at nodes of 7nm and below? The outcome will depend on whether the court finds these modern techniques to be mere improvements or fundamentally different from what the patents describe and claim.
  • A key evidentiary question for the asserted method claims will be one of process verification: what evidence can Plaintiffs present to prove that TSMC's proprietary and confidential manufacturing process follows the precise sequence of steps recited in the claims, such as the timing of a gate-cutting slot relative to epitaxial growth? This will likely require extensive and contested reverse engineering and expert testimony.
  • The case structure raises a central question of supply chain liability: with a component manufacturer (TSMC) joined with downstream product sellers (Lenovo, OnePlus), a significant issue will be the apportionment of fault and the calculation of a reasonable royalty. The court will have to consider how to value the patented technology's contribution relative to both the silicon die and the final, high-value consumer electronic device.