DCT

1:25-cv-00215

Longitude Licensing Ltd. v. Apple, Inc.

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 1:25-cv-00215, W.D. Tex., 02/13/2025
  • Venue Allegations: Plaintiffs allege venue is proper in the Western District of Texas because each Defendant maintains regular and established places of business within the district and has committed acts of patent infringement there.
  • Core Dispute: Plaintiffs allege that semiconductor devices fabricated for Defendants using advanced manufacturing processes, and the end-products incorporating them, infringe five patents related to transistor structures and fabrication methods.
  • Technical Context: The patents relate to fundamental technologies for modern high-performance semiconductors, such as strained-silicon channels and FinFET fabrication techniques, which are essential for creating smaller, faster, and more power-efficient integrated circuits.
  • Key Procedural History: The complaint alleges Plaintiffs engaged in pre-suit licensing negotiations with Apple and its supplier TSMC, beginning with a notice letter on March 8, 2023, and sent a notice letter to Broadcom on April 2, 2024. The complaint asserts these communications establish pre-suit knowledge for willfulness allegations against Apple and Broadcom, and that the filing of the complaint establishes such knowledge for Qualcomm.

Case Timeline

Date Event
2007-08-09 '847' Patent Priority Date
2010-06-29 '847 Patent Issue Date
2010-07-15 '473' Patent Priority Date
2012-02-09 '292' Patent Priority Date
2013-05-02 '747' Patent Priority Date
2015-07-28 '473 Patent Issue Date
2015-09-29 '747 Patent Issue Date
2015-11-10 '292 Patent Issue Date
2017-06-29 '880' Patent Priority Date
2018-04-24 '880 Patent Issue Date
2023-03-08 Plaintiffs' first notice letter to Apple ('847, '473)
2023-12-07 Plaintiffs' second notice letter to Apple ('292)
2024-04-02 Plaintiffs' notice letter to Broadcom ('847, '473)
2025-02-13 Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,745,847 - “Metal Oxide Semiconductor Transistor”, issued June 29, 2010

The Invention Explained

  • Problem Addressed: The patent seeks to address the ongoing challenge of increasing transistor speed by improving the mobility of charge carriers (electrons and holes) in the transistor's channel, noting that conventional methods for inducing beneficial mechanical stress in the channel have been insufficient as device dimensions shrink ('847 Patent, col. 1:11-52).
  • The Patented Solution: The invention describes a transistor structure where recesses are first etched into the semiconductor substrate on either side of the gate. Subsequently, "raised epitaxial layers" (e.g., of silicon-germanium) are grown within these recesses, rising above the original substrate surface. This process introduces strain into the transistor channel, enhancing carrier mobility. A key aspect is that the spacer on the gate's sidewall is formed after the epitaxial growth, allowing it to extend laterally over a portion of the raised layer ('847 Patent, Abstract; col. 2:39-65; FIG. 5).
  • Technical Importance: This "raised source/drain" architecture is a foundational technique in advanced semiconductor manufacturing for creating strained-silicon devices, which is critical for maintaining performance scaling (i.e., Moore's Law) in smaller process nodes ('847 Patent, col. 1:24-38).

Key Claims at a Glance

  • The complaint asserts at least independent claim 1 (Compl. ¶101).
  • Claim 1 requires:
    • A gate formed on a semiconductor substrate;
    • Two raised epitaxial layers positioned in the semiconductor substrate next to the gate and above the substrate's surface;
    • A spacer on the gate sidewall that extends laterally over a portion of the raised epitaxial layers, with the bottom of the spacer being above the substrate's surface;
    • Two doped regions formed in the semiconductor substrate next to the gate.
  • The complaint reserves the right to assert additional claims (Compl. ¶101).

U.S. Patent No. 9,093,473 - “Method for Fabricating Metal-Oxide Semiconductor Transistor”, issued July 28, 2015

The Invention Explained

  • Problem Addressed: The patent addresses a manufacturing challenge in patterning transistor gates, specifically the difficulty of etching a narrow "slot" to divide a larger gate pattern into two separate gates. The patent notes that improper etching can result in "polysilicon residue" that bridges the gates or, conversely, excessive etching that damages the protective hard mask and spacers ('473 Patent, col. 1:42-57).
  • The Patented Solution: The invention proposes a specific sequence of manufacturing steps to improve process control. It teaches forming a gate pattern, then forming an epitaxial layer in the substrate next to that pattern, and only after the epitaxial layer is in place, performing a second etching process to create the slot that separates the gate pattern. By performing the slot etch late in the sequence, the method aims to avoid the manufacturing defects associated with prior art methods ('473 Patent, Abstract; col. 4:4-25; FIG. 5).
  • Technical Importance: The claimed method provides a more robust fabrication flow for creating the dense, electrically isolated gate structures required for complex logic circuits, improving manufacturing yield by optimizing the order of critical process steps ('473 Patent, col. 5:1-11).

Key Claims at a Glance

  • The complaint asserts at least independent claim 1 (Compl. ¶114).
  • Claim 1 requires the method steps of:
    • Providing a semiconductor substrate;
    • Forming a silicon layer on the substrate;
    • Performing a first photo-etching process to form a gate pattern;
    • Forming an epitaxial layer in the substrate adjacent to the gate pattern; and
    • After forming the epitaxial layer, performing a second photo-etching process on the gate pattern to form a slot that physically separates it into two gates.
  • The complaint reserves the right to assert additional claims (Compl. ¶114).

Multi-Patent Capsule: U.S. Patent No. 9,184,292 - “Semiconductor Structure with Different Fins of FinFETs”, issued November 10, 2015

  • Technology Synopsis: This patent relates to the structure of Fin Field-Effect Transistors (FinFETs). The invention describes a semiconductor structure that integrates different types of fins on a single substrate: "odd fins" are formed from the substrate material itself, while "even fins" are formed between them using a different material or having a different width. This allows for the integration of transistors with different performance characteristics (e.g., high-power and low-leakage) on the same chip, which is crucial for modern System-on-Chip (SoC) designs ('292 Patent, Abstract; col. 3:33-51).
  • Asserted Claims: At least independent claim 1 (Compl. ¶127).
  • Accused Features: Semiconductor devices, exemplified by the Apple A15 Bionic, fabricated using TSMC's 5nm/4nm and smaller process nodes are alleged to incorporate the claimed structure with different fin types (Compl. ¶132, 134).

Multi-Patent Capsule: U.S. Patent No. 9,147,747 - “Semiconductor Structure with Hard Mask Disposed on the Gate Structure”, issued September 29, 2015

  • Technology Synopsis: This patent addresses the fabrication of electrical contacts to transistors. The invention discloses a structure where a hard mask is placed on top of the metal gate, with the top surfaces of the hard mask and the surrounding dielectric layer being at the same level. This configuration is intended to facilitate a simplified manufacturing process where the electrical contacts to the source/drain regions and the contacts to the gate can be formed simultaneously, reducing process complexity and cost ('747 Patent, Abstract; col. 2:1-10).
  • Asserted Claims: At least independent claim 1 (Compl. ¶142).
  • Accused Features: Semiconductor devices manufactured using TSMC's 3nm process node, including the Apple A17 integrated circuit and the Qualcomm Snapdragon 8 Elite, are alleged to embody the claimed structure (Compl. ¶147, 148).

Multi-Patent Capsule: U.S. Patent No. 9,953,880 - “Semiconductor Device and Method for Fabricating The Same”, issued April 24, 2018

  • Technology Synopsis: This patent discloses a method for creating an isolation structure known as a single diffusion break (SDB), which electrically isolates adjacent transistors. The claimed method involves forming fin structures and a gate layer, then etching a trench through the gate layer, the fin, and the underlying shallow trench isolation (STI). This trench is then filled with a dielectric material to form the SDB, providing robust device-to-device isolation ('880 Patent, Abstract; col. 2:47-54).
  • Asserted Claims: At least independent claim 1 (Compl. ¶155).
  • Accused Features: The manufacturing methods used for TSMC's 3nm process node, which allegedly produce devices like the Apple A17 and Qualcomm Snapdragon 8 Elite, are accused of infringing the claimed SDB formation process (Compl. ¶160, 161).

III. The Accused Instrumentality

Product Identification

The complaint targets a broad category of semiconductor devices fabricated for the Defendants by Taiwan Semiconductor Manufacturing Company (TSMC) using its 16nm and smaller process nodes (e.g., 16nm, 12nm, 7nm, 6nm, 5nm, 4nm, 3nm) (Compl. ¶62, 77, 91). Exemplary accused products include Apple's A-series and S-series processors, Broadcom's Wi-Fi SoCs and Ethernet switches, and Qualcomm's Snapdragon processors and modems, as well as the downstream consumer and enterprise products that incorporate these chips, such as iPhones, Apple Watches, smartphones, laptops, and networking hardware (Compl. ¶64-66, 79-82, 93-95).

Functionality and Market Context

The accused instrumentalities are high-performance integrated circuits that form the core processing and connectivity components of flagship electronic products. The complaint alleges that these chips are fabricated using the industry's most advanced manufacturing technologies and are central to the commercial success and functionality of Defendants' products (Compl. ¶30, 38, 46). The complaint provides an annotated image of a Broadcom product marking guide to support its allegation that a "T" code on a component identifies TSMC as the foundry (Compl. ¶107; p. 31).

IV. Analysis of Infringement Allegations

'847 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
a gate formed on a semiconductor substrate The accused devices contain a gate structure formed on a semiconductor substrate, as shown in a cross-sectional image of an Apple A15 Bionic chip. An annotated image from the complaint identifies the "Gate" structure. ¶102, 108 col. 2:62-63
two raised epitaxial layers positioned respectively in the semiconductor substrate next to the relative sides of the gate and above the surface of the semiconductor substrate The accused devices allegedly include raised source/drain regions made of silicon-germanium (SiGe) epitaxy grown in recesses next to the gate. An annotated complaint visual shows these "Epitaxial layers" rising above the substrate. ¶102, 108 col. 2:21-29
a spacer formed on the sidewall of the gate and extending laterally upon a portion of the raised epitaxial layers, and a contact surface of the raised epitaxial layers and a bottom of the spacer is above the surface of the semiconductor substrate A spacer is allegedly formed on the gate sidewall and extends over the raised epitaxial layer. The complaint includes an annotated micrograph labeling the "Spacer" and showing its position relative to the gate and epitaxial layers. ¶102, 108 col. 2:25-29
two doped region formed respectively in the semiconductor substrate next to the relative sides of the gate The complaint alleges the presence of two doped regions next to the gate, corresponding to the raised epitaxial source/drain regions which are doped during their formation (in-situ doping). ¶102, 108 col. 2:29-32

Identified Points of Contention ('847 Patent)

  • Scope Question: A central question may be whether the claim term "two doped region formed respectively in the semiconductor substrate" reads on the "two raised epitaxial layers" that constitute the source/drain regions in the accused devices. Defendants may argue that the claim recites the epitaxial layers and the doped regions as distinct elements, whereas the accused devices feature a single, merged structure. Plaintiffs may counter that the doped epitaxial layers are formed "in" recesses "within" the substrate and thus meet the limitation.
  • Technical Question: The infringement allegations rely heavily on the analysis of third-party reverse-engineering reports (e.g., from TechInsights). The accuracy of these reports and the interpretation of the provided micrographs will be a primary focus of technical discovery and expert testimony.

'473 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
...a method for fabricating a metal-oxide semiconductor (MOS) transistor, comprising: providing a semiconductor substrate; The accused devices are fabricated on a semiconductor substrate (Compl. ¶115). ¶115 col. 2:35-37
forming a silicon layer on the semiconductor substrate; performing a first photo-etching process on the silicon layer for forming a gate pattern; The accused manufacturing process allegedly involves forming a gate pattern (such as a dummy gate in a replacement gate process). The complaint provides an image showing what it labels "dummy gates" in a representative device. ¶115, 121 col. 2:44-55
forming an epitaxial layer in the semiconductor substrate adjacent to two sides of the gate pattern; The accused process allegedly forms epitaxial source/drain regions adjacent to the gate pattern. An annotated image in the complaint identifies the "Source/drain" areas. ¶115, 121 col. 4:1-3
after forming the epitaxial layer, performing a second photo-etching process on the gate pattern to form a slot...to physically separate the gate pattern into two gates. The complaint alleges that the process used to make the accused devices involves etching a slot to separate the gate pattern after the source/drain epitaxy is formed. An annotated image shows a "Slot" physically separating gate structures. ¶115, 121 col. 4:4-10

Identified Points of Contention ('473 Patent)

  • Evidentiary Question: The '473 patent claims a "method". The complaint primarily infers the sequence of manufacturing steps from images of the final, completed device structure. A key point of contention will be whether the final structure alone is sufficient evidence to prove the specific order of operations required by the claims, an issue that will depend heavily on expert analysis and discovery into TSMC's actual manufacturing processes.
  • Scope Question: The claim recites forming a slot in a "gate pattern." The accused devices are likely made using a "replacement metal gate" process, where a temporary "dummy gate" is patterned first and later replaced. The dispute will question whether etching a slot in this temporary dummy structure meets the "gate pattern" limitation as understood in the patent.

V. Key Claim Terms for Construction

'847 Patent, Claim 1

  • The Term: "two doped region formed respectively in the semiconductor substrate"
  • Context and Importance: This term is critical because the accused devices feature raised, in-situ doped epitaxial source/drain structures. The infringement analysis will turn on whether these structures, which are grown in recesses etched into the substrate, are encompassed by the claim language, or if the claim requires doped regions formed directly within the original substrate material, separate from the epitaxial layers.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The patent's objective is to create a strained channel, and the specification focuses on the role of epitaxial layers in achieving this ('847 Patent, col. 1:24-35). A party could argue that "in the semiconductor substrate" should be read broadly to include structures formed within recesses etched into that substrate, consistent with the patent's overall purpose.
    • Evidence for a Narrower Interpretation: The claim separately recites "two raised epitaxial layers" and "two doped region." A party could argue that these are structurally distinct elements and that the patent's figures show lightly doped regions (222, 224) that appear to be in the substrate itself, distinct from the subsequently formed source/drain regions (238, 240) ('847 Patent, FIG. 4, FIG. 5).

'473 Patent, Claim 1

  • The Term: "gate pattern"
  • Context and Importance: Practitioners may focus on this term because the accused devices are likely fabricated using a replacement metal gate (RMG) process, where a "dummy gate pattern" is formed first and later replaced by the final metal gate. The construction of "gate pattern" will determine whether the claim reads on processes where the critical slot-etching step is performed on this temporary dummy structure.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: A party could argue that "gate pattern" is a general term for the structure that defines the gate's location and that the patent's core invention is the "timing" of the slot etch relative to the epitaxy, not the material of the pattern being etched. The abstract describes separating "the gate pattern into two gates" without specifying its material composition ('473 Patent, Abstract).
    • Evidence for a Narrower Interpretation: The detailed description repeatedly refers to forming and patterning a "polysilicon layer" to create the gate pattern ('473 Patent, col. 2:46-47). A party could argue that "gate pattern" is therefore limited to polysilicon structures, potentially excluding dummy gates made of other materials.

VI. Other Allegations

  • Indirect Infringement: The complaint alleges both induced and contributory infringement. The inducement theory is based on Defendants designing the accused chips, knowing they would be incorporated into downstream products, and intending that such incorporation and use occur (Compl. ¶103-104, 116-117). The contributory infringement theory alleges the chips are a material part of the patented inventions, are not staple articles of commerce, and have no substantial non-infringing uses (Compl. ¶105, 118).
  • Willful Infringement: Willfulness is alleged against all Defendants. For Apple and Broadcom, the allegations are based on pre-suit notice letters and subsequent licensing discussions or lack thereof (Compl. ¶57-58, 72). For all Defendants, including Qualcomm, willfulness is alleged based on knowledge of the patents gained, at the latest, upon the filing of the complaint (Compl. ¶69, 85, 98).

VII. Analyst’s Conclusion: Key Questions for the Case

This case presents several complex technical and legal issues common in semiconductor litigation. The outcome will likely depend on the court's resolution of the following central questions:

  • A core issue will be one of "evidentiary proof for method claims": Can Plaintiffs demonstrate, based on analysis of the final chip structures, that the accused products were manufactured using the specific sequence of steps required by the asserted method patents (e.g., the '473 patent), or will direct evidence of TSMC’s manufacturing process be required?
  • A second key question will be one of "claim scope versus modern technology": Can claim terms from patents filed over a decade ago, such as "doped region... in the... substrate" ('847 patent), be construed to cover the highly integrated and structurally distinct features of modern transistors, like raised in-situ doped epitaxial source/drains?
  • Finally, a significant legal battle may arise over "joinder and liability": The complaint joins three major, competing chip designers based on their common use of a single foundry (TSMC). The case will test the theory that infringement by a shared manufacturer creates a "series of transactions or occurrences" sufficient to join unrelated defendants, and will explore how liability and damages are apportioned between the chip designers and the non-party fabricator.