DCT

3:25-cv-08588

Micron Technology Inc v. Yangtze Memory Tech Co Ltd

Log In
Key Events
Complaint

I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 3:25-cv-8588, N.D. Cal., 10/07/2025
  • Venue Allegations: Plaintiffs (collectively "Micron") allege venue is proper in the Northern District of California because Defendant (YMTC) is subject to personal jurisdiction in the district through its own acts and those of its wholly-owned subsidiary, YMTI, which has an established place of business in Santa Clara, CA. Micron asserts that YMTC has purposely availed itself of the laws of California through business activities, sales, and prior litigation in the district.
  • Core Dispute: Micron seeks a declaratory judgment that its 3D-NAND and DRAM memory products do not infringe eight U.S. patents owned by YMTC.
  • Technical Context: The dispute centers on semiconductor memory technology, specifically high-density 3D NAND flash memory and high-speed Double Data Rate (DDR) DRAM, which are fundamental components for data storage and processing in virtually all modern electronic devices.
  • Key Procedural History: This declaratory judgment action was filed by Micron in response to an infringement suit YMTC filed against Micron and others in the Eastern District of Texas (referred to as "Yangtze III") asserting the same eight patents. Micron contends that venue in the Texas action is improper. This filing appears to be a strategic maneuver to secure a different forum. The complaint also notes two prior patent suits filed by YMTC against Micron in the Northern District of California ("Yangtze I" and "Yangtze II"), which were stayed pending inter partes review proceedings at the U.S. Patent Trial and Appeal Board.

Case Timeline

Date Event
2015-03-XX Micron launches its first 32-layer 3D NAND product
2016-XX-XX Defendant YMTC is founded
2018-Early Micron releases its 64-layer 3D NAND product
2018-08-XX YMTC launches its Xtacking® architecture
2019-05-05 Priority Date for ’851 Patent
2019-XX-XX Micron samples its 128-layer 3D NAND product
2019-12-24 Priority Date for ’250 Patent
2020-XX-XX Micron launches its 176-layer 3D NAND product
2020-03-23 Priority Date for ’313 Patent
2020-04-27 Priority Date for ’066 Patent
2020-05-06 Priority Date for ’925 Patent
2020-07-07 U.S. Patent No. 10,707,851 Issues
2021-XX-XX Micron releases its 1α node-based DRAM products
2021-05-17 Priority Date for ’403 Patent
2021-05-28 Priority Date for ’621 Patent
2021-12-22 Priority Date for ’767 Patent
2022-01-25 U.S. Patent No. 11,233,066 Issues
2022-07-XX Micron scales its 3D NAND technology to 232-layers
2023-10-25 Plaintiff Micron Technology Texas, LLC is dissolved
2023-11-XX YMTC files Yangtze I suit against Micron in N.D. Cal.
2024-07-XX YMTC files Yangtze II suit against Micron in N.D. Cal.
2024-08-20 U.S. Patent No. 12,068,250 Issues
2024-08-27 U.S. Patent No. 12,075,621 Issues
2024-09-17 U.S. Patent No. 12,094,767 Issues
2025-02-18 U.S. Patent No. 12,232,313 Issues
2025-03-XX Yangtze I and Yangtze II suits are stayed pending IPR
2025-03-18 U.S. Patent No. 12,254,925 Issues
2025-04-01 U.S. Patent No. 12,266,403 Issues
2025-10-07 Complaint for Declaratory Judgment filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 11,233,066 - "Three-Dimensional Memory Device and Method for Forming the Same," issued January 25, 2022

The Invention Explained

  • Problem Addressed: As semiconductor manufacturers transitioned from planar (2D) to 3D memory architectures to increase data density, new fabrication challenges arose. The patent background notes that certain manufacturing techniques, such as sidewall selective epitaxial growth (SEG) for forming semiconductor plugs, suffer from process variations and can complicate device operation (e.g., requiring a P-well for bulk erase operations) (’066 Patent, col. 3:55-4:25).
  • The Patented Solution: The patent describes a 3D memory device structure that includes a specialized "source contact structure." This structure is designed with a wider base (a "first lateral dimension") where it is surrounded by a doped region in the substrate, and a narrower upper portion where it is surrounded by the memory stack (’066 Patent, Abstract). This configuration is intended to enable a more reliable "GIDL-assisted body biasing" for erase operations, eliminating the need for a P-well and simplifying device control (’066 Patent, col. 4:26-39). The overall structure is depicted in Figure 1 of the patent.
  • Technical Importance: This design aims to improve the reliability and manufacturability of high-density 3D NAND memory by simplifying the control logic for erase operations, a critical factor for scaling memory devices to higher layer counts.

Key Claims at a Glance

  • The complaint identifies independent claims 1, 13, and 15 as asserted (Compl. ¶43).
  • Independent claim 1, a focus of the complaint, includes these essential elements:
    • A three-dimensional (3D) memory device, comprising:
    • an N-type doped region of a substrate;
    • an N-type doped semiconductor layer on the N-type doped region;
    • a memory stack comprising interleaved conductive layers and dielectric layers;
    • a channel structure extending vertically through the memory stack and into the N-type doped region; and
    • a source contact structure extending vertically through the memory stack and into the N-type doped region, wherein a first lateral dimension of a first portion of the source contact structure is greater than a second lateral dimension of a second portion of the source contact structure.

U.S. Patent No. 12,068,250 - "3D NAND Memory Device and Method of Forming the Same," issued August 20, 2024

The Invention Explained

  • Problem Addressed: The patent addresses the challenge of creating electrical connections to the many vertically stacked word lines in a 3D NAND device. This is typically achieved by forming a terraced or "staircase" structure at the edge of the memory array, but conventional designs can be complex to manufacture as layer counts increase (’250 Patent, col. 1:15-24, col. 5:5-12).
  • The Patented Solution: The invention discloses a specific semiconductor device architecture with a unique connection region between two memory arrays. This region contains two distinct staircase structures. The patent focuses on a "first staircase" that has two sets of stairs: one group with a "first step-down direction" and a second group with an "opposite" second step-down direction, causing them to converge toward a low point (’250 Patent, Abstract; Fig. 4A). This V-shaped staircase configuration is intended to manage the complex routing of contacts to the word line layers.
  • Technical Importance: This architectural approach suggests a method to manage the manufacturing complexity and electrical performance of the contact region in very high layer count 3D NAND devices, which is a critical area for innovation and competition.

Key Claims at a Glance

  • The complaint identifies independent claim 1 as asserted (Compl. ¶55).
  • Independent claim 1 includes these essential elements:
    • A semiconductor device, comprising:
    • a stack of word line layers and insulating layers;
    • channel structures formed in a first array region and a second array region of the stack, positioned at opposing sides;
    • wherein a first staircase is formed between the array regions;
    • a second staircase is formed between the array regions;
    • a portion of the stack is positioned between the first and second staircase;
    • the first staircase has first stairs with a first step-down direction and second stairs with a second step-down direction, the first step-down direction being opposite to the second step-down direction.

Multi-Patent Capsules

  • U.S. Patent No. 12,094,767, "Barrier Layers for Word Line Contacts in a Three-Dimensional NAND Memory and Fabrication Methods Thereof," issued September 17, 2024

    • Technology Synopsis: The patent describes a memory device structure with multiple barrier layers on a staircase structure to protect certain layers during etching processes. The invention specifies a "second barrier layer" that is "distant from the GLS [gate line slit]" in a particular direction, suggesting a design to improve manufacturing precision by creating a selective etch stop (’767 Patent, Abstract).
    • Asserted Claims: Independent claim 1 (Compl. ¶67).
    • Accused Features: Micron’s 176-layer, 232-layer, and 276-layer 3D NAND devices are accused. Micron alleges its products do not have the claimed "second barrier layer... distant from the GLS" in the specified orientation (Compl. ¶71).

  • U.S. Patent No. 12,075,621, "Three-Dimensional Memory Device and Method for Forming the Same," issued August 27, 2024

    • Technology Synopsis: This patent details a 3D memory device where the drain select gate line and the word lines are made of the same material and are in direct contact with the semiconductor channel and memory film, respectively. This configuration aims to simplify the manufacturing process and improve device performance (’621 Patent, Abstract).
    • Asserted Claims: Independent claims 1 and 9 (Compl. ¶79).
    • Accused Features: Micron’s 176-layer, 232-layer, and 276-layer 3D NAND devices are accused. Micron alleges its products do not have a drain select gate line in direct contact with the semiconductor channel or word lines in direct contact with the memory film as required by the claims (Compl. ¶83).

  • U.S. Patent No. 12,232,313, "Staircase Structure in Three-Dimensional Memory Device and Method for Forming the Same," issued February 18, 2025

    • Technology Synopsis: The patent describes a complex staircase structure with "first sub-staircases and second sub-staircases arranged alternately." The first sub-staircases have ascending stairs at different depths, while the second have descending stairs at different depths. This intricate geometry is designed to manage contacts in a high-density 3D memory array (’313 Patent, Abstract).
    • Asserted Claims: Independent claims 1, 8, and 16 (Compl. ¶91).
    • Accused Features: Micron’s 176-layer, 232-layer, and 276-layer 3D NAND devices are accused. Micron contends its products do not have the claimed alternately arranged sub-staircases with different ascending and descending depths (Compl. ¶95).

  • U.S. Patent No. 12,266,403, "Three-Dimensional NAND Memory and Fabrication Method Thereof," issued April 1, 2025

    • Technology Synopsis: This patent claims a method for fabricating a 3D memory device. The method involves forming multiple dielectric stacks, an etch-stop layer, and then replacing certain dielectric layers with conductive layers through a gate line slit (GLS) opening to form a top select gate and other film stacks (’403 Patent, Abstract).
    • Asserted Claims: Independent claims 1, 11, and 20 (Compl. ¶103).
    • Accused Features: Micron’s 176-layer, 232-layer, and 276-layer 3D NAND devices are accused. As this is a method patent, Micron alleges its manufacturing processes do not perform the claimed steps, such as "forming an etch-stop layer on the second dielectric stack" (Compl. ¶107).

  • U.S. Patent No. 12,254,925, "Control Method and Controller of 3D NAND Flash," issued March 18, 2025

    • Technology Synopsis: This patent relates to a method for programming a memory cell. It claims a sequence of applying program pulses where a "last program pulse" has a pulse width that is wider than the pulse width of preceding "middle program pulses" and the "first program pulse." This technique is intended to control the programming characteristics of the memory cell (’925 Patent, Abstract).
    • Asserted Claims: Independent claims 1 and 11 (Compl. ¶115).
    • Accused Features: Micron’s 176-layer, 232-layer, and 276-layer 3D NAND devices are accused. Micron alleges its programming methods do not use a final program pulse with a wider pulse width as required by the claim (Compl. ¶119).

  • U.S. Patent No. 10,707,851, "Double Data Rate Circuit and Data Generation Method Implementing Precise Duty Cycle Control," issued July 7, 2020

    • Technology Synopsis: The patent describes a double data rate (DDR) circuit for high-speed data transmission, relevant to DRAM. It claims a specific circuit implementation for a multiplexer that combines multiple data bits into an output stream, specifying that it comprises "four 3-input NAND gates and one 4-input NAND gate coupled thereto" to achieve precise duty cycle control (’851 Patent, Abstract).
    • Asserted Claims: Independent claims 1, 8, and 15 (Compl. ¶127).
    • Accused Features: Micron’s Low-Power DDR5 and DDR5X DRAM devices are accused. Micron alleges its products do not use a multiplexer with the specific four 3-input and one 4-input NAND gate configuration required by the claims (Compl. ¶131).

III. The Accused Instrumentality

Product Identification

  • Plaintiffs’ own "3D-NAND and DRAM memory products" (Compl. ¶16). Specifically named product categories are "Micron 176-layer, 232-layer, and 276-layer 3D NAND devices" and "Micron Low-Power DDR5 DRAM and Low-Power DDR5X DRAM devices" (Compl. ¶¶ 46, 130).

Functionality and Market Context

  • The complaint positions Micron as the "only United States founded memory semiconductor designer and manufacturer" and a "world leader" in the field (Compl. ¶2). It details a history of innovation, progressing from 32-layer 3D NAND in 2015 to 232-layer production in 2022, and developing advanced DRAM process technologies (Compl. ¶¶4-6). These allegations establish the accused products as commercially significant, high-volume, and technologically advanced components in the global semiconductor market. No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

U.S. Patent No. 11,233,066 Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Non-Infringing Functionality Complaint Citation Patent Citation
a source contact structure extending vertically... wherein: a first lateral dimension of a first portion of the source contact structure surrounded by the N-type doped region is greater than a second lateral dimension of a second portion of the source contact structure surrounded by the memory stack; and Micron's 176-layer, 232-layer, and 276-layer 3D NAND devices do not have a source contact structure with the claimed dimensional relationships between its different vertical portions. ¶47 col. 8:5-17
a third lateral dimension of a third portion of the source contact structure surrounded by the N-type doped semiconductor layer is greater than the second lateral dimension of the second portion of the source contact structure. Micron's devices do not satisfy these specific geometric constraints for the source contact structure. ¶47 col. 8:18-22
  • Identified Points of Contention:
    • Factual/Technical Question: The central dispute will be a factual one based on the physical structure of Micron's devices. The court will need to determine if the component in Micron's chips that functions as a "source contact structure" actually has the specific tiered-width geometry required by claim 1—namely, a base that is wider than its middle/upper portions in the claimed manner. This analysis will likely depend on expert testimony interpreting cross-sectional scanning electron microscope (SEM) images of the accused chips.
    • Scope Question: A related question is one of claim scope: how are the "first portion," "second portion," "third portion," and their respective "lateral dimensions" defined and measured? The parties may dispute the precise boundaries of these portions and the methodology for measuring their dimensions, which will be a matter for claim construction.

U.S. Patent No. 12,068,250 Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Non-Infringing Functionality Complaint Citation Patent Citation
channel structures formed in a first array region and a second array region of the stack, the first array region and the second array region being positioned at opposing sides of the stack Micron's devices do not have channel structures in array regions positioned on "opposing sides of the stack" in the manner required by the claim. ¶59 col. 10:22-26
the first staircase has first stairs with a first step-down direction and second stairs with a second step-down direction, the first step-down direction being opposite to the second step-down direction Micron's devices do not utilize a staircase structure where stairs step down in opposite directions to form the claimed V-shaped or converging geometry. ¶59 col. 11:1-4
  • Identified Points of Contention:
    • Structural Question: The dispute will likely focus on the physical layout of the staircase region in Micron’s NAND devices. The question for the court will be whether Micron's design incorporates a single "staircase" that includes two sets of stairs descending in opposite directions, as claimed. Micron's allegation suggests its architecture uses a different, non-infringing configuration to achieve word line contacts.
    • Definitional Scope: Claim construction may focus on the phrase "the first staircase." Does this term refer to the entire terraced structure in the connection region, or can it refer to a sub-part of it? How the court defines the boundaries of the "first staircase" will be critical to determining if it contains stairs with "opposite" step-down directions.

V. Key Claim Terms for Construction

From the ’066 Patent:

  • The Term: "a first lateral dimension... is greater than a second lateral dimension"
  • Context and Importance: This relational limitation lies at the heart of Micron's non-infringement argument for the '066 patent. The entire dispute for claim 1 turns on whether this specific geometry exists in the accused products. Practitioners may focus on this term because its interpretation—specifically, where and how the "lateral dimensions" of the different "portions" of the source contact structure are measured—will be dispositive.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The patent does not appear to provide an explicit definition that would broaden the term beyond its plain meaning. A party might argue that any measurable difference, however slight, satisfies the "greater than" requirement.
    • Evidence for a Narrower Interpretation: The figures, particularly Figure 1, show a distinct and visually significant difference in width between the lower portion (132) and the upper portions (133, 134) of the source contact structure 122 (’066 Patent, Fig. 1). A party could argue that this depiction limits the claim to structures with a similarly clear and intentional tiered design, not merely incidental process variations.

From the ’250 Patent:

  • The Term: "the first staircase has first stairs... and second stairs... the first step-down direction being opposite to the second step-down direction"
  • Context and Importance: This term describes a unique V-shaped or converging staircase geometry that Micron alleges is absent from its products. The construction of what constitutes a single "staircase" and what it means for step-down directions to be "opposite" within it is central to the infringement question for the '250 patent.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: A party might argue that "opposite" does not require perfect 180-degree opposition, but could encompass any two sets of stairs that generally descend toward each other from different sides of the connection region.
    • Evidence for a Narrower Interpretation: The specification describes the first and second groups of stairs as "converging at a first shared stair" (’250 Patent, col. 2:48-50). Figure 4A clearly illustrates two sets of stairs (402A, 402B) descending in opposite x-directions to meet at a low point (408). This could support an interpretation requiring a distinct, converging V-shape within a single, identifiable "staircase."

VI. Other Allegations

  • Indirect Infringement: The complaint seeks a declaratory judgment of non-infringement of all asserted patents "either directly under 35 U.S.C. § 271(a), (g) or indirectly under 35 U.S.C. § 271(b)–(c)" (e.g., Compl. ¶51). As a declaratory judgment action, the complaint does not allege facts supporting an indirect infringement claim but rather preemptively denies liability for it.
  • Willful Infringement: Willfulness is not at issue in this declaratory judgment complaint. However, Micron does ask the Court to find that this is an "exceptional case under 35 U.S.C. § 285" and award attorneys' fees, suggesting Micron believes YMTC's assertion of the patents is baseless or constitutes litigation misconduct (Compl. p. 24).

VII. Analyst’s Conclusion: Key Questions for the Case

This declaratory judgment action appears primarily driven by a dispute over venue, with Micron seeking to litigate in the Northern District of California rather than the Eastern District of Texas where YMTC filed suit. Substantively, the case will likely turn on the following core questions:

  • A central issue will be one of structural correspondence: Do Micron’s high-volume 3D NAND and DRAM products, which it presents as the result of its own long-standing innovation, contain the highly specific and intricate circuit layouts, staircase geometries, and material compositions recited in YMTC’s patents? The non-infringement arguments for the '066, '250, '313, '621, '767, and '851 patents all hinge on alleged mismatches in physical structure.
  • A key evidentiary question will be one of operational correspondence: Does Micron's method for programming its NAND devices utilize the specific pulse-width modulation scheme required by the '925 patent, and do its manufacturing methods for those devices follow the precise sequence of steps claimed in the '403 patent? These disputes will require a comparison of YMTC's claimed methods against Micron's actual, proprietary processes.
  • Looming over the technical dispute is the procedural question of forum: The case's initiation as a declaratory judgment action to counter a suit in another district suggests that a primary battleground, preceding any technical analysis, will be over which court—California or Texas—is the proper venue to decide these infringement questions.