DCT

5:25-cv-08588

Micron Technology Inc v. Yangtze Memory Tech Co Ltd

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Key Events
Complaint

I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 5:25-cv-08588, N.D. Cal., 10/07/2025
  • Venue Allegations: Plaintiff alleges venue is proper in the Northern District of California because Defendant is subject to personal jurisdiction in the district. The complaint bases this on Defendant’s wholly-owned California subsidiary (YMTI), Defendant’s business activities, sales to customers like Apple within the district, and its history of filing patent litigation in the district.
  • Core Dispute: Plaintiff seeks a declaratory judgment that its 3D-NAND and DRAM memory products do not infringe eight U.S. patents owned by Defendant.
  • Technical Context: The dispute centers on semiconductor memory technology, specifically the architecture and operation of high-density 3D NAND flash memory and Double Data Rate (DDR) DRAM circuits, which are fundamental components in modern computing, mobile devices, and data centers.
  • Key Procedural History: This action follows three prior infringement suits filed by Defendant YMTC against Plaintiff Micron. Two suits filed in the Northern District of California ("Yangtze I" and "Yangtze II") were stayed in March 2025 pending inter partes review of the asserted patents. This declaratory judgment action was filed in response to a third suit ("Yangtze III") that YMTC filed against Micron in the Eastern District of Texas concerning the eight patents-in-suit analyzed in this report.

Case Timeline

Date Event
2019-05-05 U.S. Patent No. 10,707,851 Priority Date
2019-12-24 U.S. Patent No. 12,068,250 Priority Date
2020-03-23 U.S. Patent No. 12,232,313 Priority Date
2020-04-27 U.S. Patent No. 11,233,066 Priority Date
2020-05-06 U.S. Patent No. 12,254,925 Priority Date
2020-07-07 U.S. Patent No. 10,707,851 Issues
2021-05-17 U.S. Patent No. 12,266,403 Priority Date
2021-05-28 U.S. Patent No. 12,075,621 Priority Date
2021-12-22 U.S. Patent No. 12,094,767 Priority Date
2022-01-25 U.S. Patent No. 11,233,066 Issues
2023-11-XX Yangtze I litigation filed by YMTC against Micron
2024-07-XX Yangtze II litigation filed by YMTC against Micron
2024-08-20 U.S. Patent No. 12,068,250 Issues
2024-08-27 U.S. Patent No. 12,075,621 Issues
2024-09-17 U.S. Patent No. 12,094,767 Issues
2025-02-18 U.S. Patent No. 12,232,313 Issues
2025-03-XX Yangtze I and Yangtze II litigations stayed pending IPR
2025-03-18 U.S. Patent No. 12,254,925 Issues
2025-04-01 U.S. Patent No. 12,266,403 Issues
2025-10-07 Complaint for Declaratory Judgment Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 11,233,066 - "Three-Dimensional Memory Device and Method for Forming the Same"

  • Patent Identification: U.S. Patent No. 11233066, "Three-Dimensional Memory Device and Method for Forming the Same," issued January 25, 2022.

The Invention Explained

  • Problem Addressed: The patent describes challenges in fabricating high-density 3D NAND memory. Specifically, conventional methods using P-well bulk erase operations require complex controls to form an inversion channel for reading, and fabricating "sidewall SEG" (selective epitaxial growth) plugs can suffer from variations due to surface residues on the semiconductor channels (’066 Patent, col. 4:14-24).
  • The Patented Solution: The invention proposes a 3D memory architecture that eliminates the P-well. It uses an N-type doped semiconductor layer deposited on an N-type doped region of the substrate. This structure allows for GIDL (gate-induced-drain-leakage)-assisted body biasing during erase operations, which simplifies the control of the source select gate (’066 Patent, col. 4:25-40). The invention also features a specific geometry for the source contact structure, where the lower portion is wider than the upper portion, which may facilitate alignment during fabrication (’066 Patent, col. 8:5-18, FIG. 1).
  • Technical Importance: This design aims to simplify fabrication and device operation by providing an alternative to complex P-well erase mechanisms and avoiding the process variability associated with sidewall SEG techniques (’066 Patent, col. 4:35-40).

Key Claims at a Glance

  • The complaint identifies independent claims 1, 13, and 15, focusing its non-infringement argument on claim 1 (Compl. ¶43, ¶47).
  • Independent Claim 1 requires:
    • A three-dimensional (3D) memory device, comprising:
    • an N-type doped region of a substrate;
    • an N-type doped semiconductor layer on the N-type doped region;
    • a memory stack with interleaved conductive and dielectric layers on the N-type doped semiconductor layer;
    • a channel structure extending vertically through the memory stack and semiconductor layer into the doped region; and
    • a source contact structure extending vertically through the memory stack and semiconductor layer into the doped region, wherein:
    • a first lateral dimension of a first portion of the source contact structure (surrounded by the N-type doped region) is greater than a second lateral dimension of a second portion of the source contact structure (surrounded by the memory stack); and
    • a third lateral dimension of a third portion of the source contact structure (surrounded by the N-type doped semiconductor layer) is greater than the second lateral dimension of the second portion.
  • The complaint does not explicitly reserve the right to assert dependent claims but seeks a declaration of non-infringement of the entire patent (Compl. ¶51).

U.S. Patent No. 12,068,250 - "3D NAND Memory Device and Method of Forming the Same"

  • Patent Identification: U.S. Patent No. 12068250, "3D NAND Memory Device and Method of Forming the Same," issued August 20, 2024.

The Invention Explained

  • Problem Addressed: As 3D NAND flash memory layer counts increase to enhance density, the complexity of fabricating the "staircase" structures used to contact each word line also increases, involving multiple complex and time-consuming processing steps (’250 Patent, col. 5:5-15).
  • The Patented Solution: The patent discloses a specific semiconductor device architecture where two separate staircase structures are formed in a connection region situated between two memory array regions. The key feature is that the first staircase has two sets of stairs ("first stairs" and "second stairs") with step-down directions that are "opposite to" each other, converging at a shared stair (’250 Patent, col. 1:47 - col. 2:2; FIG. 4A). This design is intended to simplify the manufacturing process.
  • Technical Importance: This dual-staircase architecture with opposing step-down directions is proposed as a way to simplify the manufacturing process, potentially by reducing the number of required mask and etching steps needed to form contacts for all word lines in a high-density device (’250 Patent, col. 4:45-50).

Key Claims at a Glance

  • The complaint asserts independent claim 1 (Compl. ¶55).
  • Independent Claim 1 requires:
    • A semiconductor device, comprising:
    • a stack of word line layers and insulating layers stacked alternatingly; and
    • channel structures formed in a first array region and a second array region of the stack, with the regions positioned at opposing sides of the stack; wherein
    • a first staircase is formed between the array regions;
    • a second staircase is formed between the array regions;
    • a portion of the stack is positioned between the staircases;
    • the first staircase has first stairs with a first step-down direction and second stairs with a second step-down direction, where the first step-down direction is opposite to the second; and
    • each of the first and second stairs corresponds to a different word line layer.
  • The complaint seeks a declaration of non-infringement for the entire patent (Compl. ¶63).

U.S. Patent No. 12,094,767 - "Barrier Layers for Word Line Contacts in a Three-Dimensional NAND Memory and Fabrication Methods Thereof"

  • Patent Identification: U.S. Patent No. 12094767, "Barrier Layers for Word Line Contacts in a Three-Dimensional NAND Memory and Fabrication Methods Thereof," issued September 17, 2024.
  • Technology Synopsis: This patent addresses the fabrication of 3D NAND memory, focusing on preventing "over-etching" when creating contacts to word lines in a staircase structure. The proposed solution involves disposing a second barrier layer, different from a first barrier layer, in a specific region of the staircase structure that is "distant" from the gate line slit (GLS), thereby providing a durable etch stop (’767 Patent, Abstract).
  • Asserted Claims: The complaint asserts independent claim 1 (Compl. ¶67).
  • Accused Features: Plaintiff's 176-layer, 232-layer, and 276-layer 3D NAND devices are accused of infringement (Compl. ¶70). The non-infringement argument focuses on the absence of the claimed "second barrier layer" with its specific positional relationship to the GLS (Compl. ¶71).

U.S. Patent No. 12,075,621 - "Three-Dimensional Memory Device and Method for Forming the Same"

  • Patent Identification: U.S. Patent No. 12075621, "Three-Dimensional Memory Device and Method for Forming the Same," issued August 27, 2024.
  • Technology Synopsis: This patent describes a 3D memory device architecture where the drain select gate line and the plurality of word lines are made of the same material. Critically, the drain select gate line is in "direct contact" with the semiconductor channel, while each of the word lines is in "direct contact" with the memory film surrounding the channel (’621 Patent, Abstract).
  • Asserted Claims: The complaint asserts independent claims 1 and 9 (Compl. ¶79).
  • Accused Features: Plaintiff's 176-layer, 232-layer, and 276-layer 3D NAND devices are accused of infringement (Compl. ¶82). The non-infringement argument centers on the devices not meeting the "direct contact" requirements for both the drain select gate line and the word lines (Compl. ¶83).

U.S. Patent No. 12,232,313 - "Staircase Structure in Three-Dimensional Memory Device and Method for Forming the Same"

  • Patent Identification: U.S. Patent No. 12232313, "Staircase Structure in Three-Dimensional Memory Device and Method for Forming the Same," issued February 18, 2025.
  • Technology Synopsis: This patent details a complex staircase architecture for 3D memory. It features two "staircase zones" separated by bridge structures. Each zone comprises alternating "first sub-staircases" with ascending stairs and "second sub-staircases" with descending stairs at different depths, creating an intricate, interleaved structure for word line connections (’313 Patent, Abstract).
  • Asserted Claims: The complaint asserts independent claims 1, 8, and 16 (Compl. ¶91).
  • Accused Features: Plaintiff's 176-layer, 232-layer, and 276-layer 3D NAND devices are accused of infringement (Compl. ¶94). The non-infringement assertion is based on the devices lacking the claimed alternating arrangement of ascending and descending sub-staircases (Compl. ¶95).

U.S. Patent No. 12,266,403 - "Three-Dimensional NAND Memory and Fabrication Method Thereof"

  • Patent Identification: U.S. Patent No. 12266403, "Three-Dimensional NAND Memory and Fabrication Method Thereof," issued April 1, 2025.
  • Technology Synopsis: This patent discloses a method for forming a 3D memory device. The method involves forming two separate dielectric stacks, one on top of the other, forming an etch-stop layer on the top stack, and then using a gate line slit (GLS) opening to replace certain dielectric layers with conductive layers to form the top select gate and other film stacks (’403 Patent, Abstract).
  • Asserted Claims: The complaint asserts independent claims 1, 11, and 20 (Compl. ¶103).
  • Accused Features: Plaintiff's 176-layer, 232-layer, and 276-layer 3D NAND devices are accused of being made by an infringing process (Compl. ¶106). The complaint denies this, stating the manufacturing process does not satisfy key steps like "forming a second dielectric stack" and "forming an etch-stop layer on the second dielectric stack" as claimed (Compl. ¶107).

U.S. Patent No. 12,254,925 - "Control Method and Controller of 3D NAND Flash"

  • Patent Identification: U.S. Patent No. 12254925, "Control Method and Controller of 3D NAND Flash," issued March 18, 2025.
  • Technology Synopsis: This patent describes a method for programming a memory cell using a sequence of voltage pulses. The method specifies that after a first program pulse, "middle program pulses" are applied, and finally a "last program pulse" is applied. The claimed novelty lies in the pulse widths: the last pulse is wider than the middle pulses, and the first middle pulse is wider than the initial first pulse (’925 Patent, Abstract).
  • Asserted Claims: The complaint asserts independent claims 1 and 11 (Compl. ¶115).
  • Accused Features: Plaintiff's 176-layer, 232-layer, and 276-layer 3D NAND devices are accused of infringement (Compl. ¶118). The non-infringement argument focuses on the devices not using a programming method where the "pulse width of the last program pulse is wider than" the preceding pulses (Compl. ¶119).

U.S. Patent No. 10,707,851 - "Double Data Rate Circuit and Data Generation Method Implementing Precise Duty Cycle Control"

  • Patent Identification: U.S. Patent No. 10707851, "Double Data Rate Circuit and Data Generation Method Implementing Precise Duty Cycle Control," issued July 7, 2020.
  • Technology Synopsis: This patent relates to DDR (Double Data Rate) circuits. The invention describes a specific circuit design for a multiplexer used to combine multiple data bits into a high-speed output stream. The claimed circuit explicitly comprises four 3-input NAND gates and one 4-input NAND gate, coupled and configured to generate the output based on multiphase clock signals (’851 Patent, Abstract).
  • Asserted Claims: The complaint asserts independent claims 1, 8, and 15 (Compl. ¶127).
  • Accused Features: Plaintiff's Low-Power DDR5 and DDR5X DRAM devices are accused of infringement (Compl. ¶130). The complaint denies infringement based on the assertion that the multiplexers in Micron's products do not use the specific claimed combination of four 3-input NAND gates and one 4-input NAND gate (Compl. ¶131).

III. The Accused Instrumentality

Product Identification

  • The accused instrumentalities are Plaintiff Micron's 176-layer, 232-layer, and 276-layer 3D NAND flash memory devices, and its Low-Power DDR5 and Low-Power DDR5X DRAM memory devices (Compl. ¶¶ 46, 130).

Functionality and Market Context

  • The accused products are high-performance semiconductor memory components. The 3D NAND devices provide high-density non-volatile storage, while the DRAM devices provide high-speed volatile memory for computing systems (Compl. ¶¶ 4-6). The complaint positions Micron as a U.S.-based global leader and innovator in these technologies, which are critical for applications ranging from consumer electronics to artificial intelligence infrastructure (Compl. ¶2). The complaint notes that Micron has been a pioneer in scaling 3D NAND technology to higher layer counts, launching its 176-layer product in 2020 and its 232-layer product in 2022 (Compl. ¶¶1-2). No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

11,233,066 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Non-Infringing Functionality Complaint Citation Patent Citation
a first lateral dimension of a first portion of the source contact structure surrounded by the N-type doped region is greater than a second lateral dimension of a second portion of the source contact structure surrounded by the memory stack Plaintiff asserts its 176-layer, 232-layer, and 276-layer 3D NAND devices do not satisfy this claim element. ¶47 col. 16:1-5
a third lateral dimension of a third portion of the source contact structure surrounded by the N-type doped semiconductor layer is greater than the second lateral dimension of the second portion of the source contact structure Plaintiff asserts its accused 3D NAND devices do not satisfy this claim element. ¶47 col. 16:6-11

12,068,250 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Non-Infringing Functionality Complaint Citation Patent Citation
channel structures formed in a first array region and a second array region of the stack, the first array region and the second array region being positioned at opposing sides of the stack Plaintiff asserts its 176-layer, 232-layer, and 276-layer 3D NAND devices do not satisfy this structural limitation. ¶59 col. 13:10-14
the first staircase has first stairs with a first step-down direction and second stairs with a second step-down direction, the first step-down direction being opposite to the second step-down direction Plaintiff asserts its accused 3D NAND devices do not satisfy this limitation regarding the structure and orientation of the staircase stairs. ¶59 col. 14:24-28
  • Identified Points of Contention:
    • Scope Questions: For the ’066 patent, the dispute may center on the construction of terms such as "first portion," "second portion," and "third portion" of the source contact structure. How these regions are defined will determine where the "lateral dimension" is measured and whether the claimed "greater than" relationship exists. For the ’250 patent, the construction of "opposing sides of the stack" and "opposite" step-down directions will be critical. The court will need to determine if these terms require a specific, mirrored, or symmetrical layout that Plaintiff's products may not possess.
    • Technical Questions: A primary technical question for the ’066 patent will be one of metrology: what evidence can be presented to definitively measure and compare the lateral dimensions of the specified portions of the source contact structure within Micron's sub-micron scale devices? For the ’250 patent, the question will be a factual comparison of the physical layout of Micron's staircase structures against the claimed architecture, once the key terms are construed.

V. Key Claim Terms for Construction

Patent: U.S. 11,233,066

  • The Term: "a first lateral dimension...is greater than a second lateral dimension"
  • Context and Importance: This limitation defines the core geometric novelty of the claimed source contact structure. Plaintiff's non-infringement position is directly tied to its products allegedly not meeting this dimensional requirement (Compl. ¶47). Practitioners may focus on this term because the entire infringement question for this patent could hinge on the methodology for measuring and comparing these dimensions.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The claim language itself does not specify a measurement methodology or a required magnitude of difference, which might support an argument that any measurable difference suffices.
    • Evidence for a Narrower Interpretation: The patent figures, such as FIG. 1, depict a source contact structure (122) with a visually distinct and significantly wider lower portion (132) compared to its upper portion (134) (’066 Patent, FIG. 1). The abstract also states the first lateral dimension "is greater than" the second, suggesting a clear and intended structural difference, not an incidental process variation.

Patent: U.S. 12,068,250

  • The Term: "the first step-down direction being opposite to the second step-down direction"
  • Context and Importance: This term is central to the claimed staircase architecture, which is the basis for the patent's asserted novelty. Plaintiff's non-infringement argument relies on its devices not having this specific configuration (Compl. ¶59). The definition of "opposite" will determine whether the claim requires a specific 180-degree directional opposition or allows for other non-aligned configurations.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: In a general sense, "opposite" could be argued to mean merely "different" or "not the same," potentially broadening the claim's scope.
    • Evidence for a Narrower Interpretation: The patent's detailed description and figures, such as FIG. 4A, show a first group of stairs (402A) stepping down in the +X direction and a second group of stairs (402B) stepping down in the -X direction, converging at a central point (408) (’250 Patent, FIG. 4A; col. 7:17-25). This strong visual evidence suggests "opposite" is intended to mean directions that are directly contrary, such as along the same axis but in different directions.

VI. Other Allegations

  • Indirect Infringement: The complaint seeks a declaration of non-infringement for both direct and indirect infringement under 35 U.S.C. § 271(b)-(c) for all asserted patents. The basis for this request is the allegation that because Micron's products do not directly infringe any claim, neither Micron nor its customers can be liable for indirect infringement, which requires an underlying act of direct infringement (Compl. ¶¶ 51, 63, 75, 87, 99, 111, 123, 135).

VII. Analyst’s Conclusion: Key Questions for the Case

  • A central issue will be one of structural and geometric correspondence: Do the physical architectures of Micron’s accused 3D NAND devices embody the specific dimensional relationships for source contacts (’066 Patent) and the precise layouts for multi-zone, opposing-direction staircases (’250, ’313 Patents) required by a plain reading of the claims and their supporting specifications?
  • A key technical question for the DRAM-related patent will be one of circuit-level implementation: Does the multiplexer circuitry in Micron’s DDR5 products utilize the exact combination of four 3-input and one 4-input NAND gates as recited in claim 1 of the ’851 patent, or does it achieve a similar function through a materially different circuit design?
  • A procedural question underlying the entire dispute is one of forum and strategy: This declaratory judgment action in California, a venue favored by Micron, directly counters Defendant’s infringement suit in Texas. The outcome of early motions related to jurisdiction and venue may significantly influence the trajectory and leverage of the parallel litigations.