DCT

2:25-cv-01010

Yangtze Memory Technologies Co Ltd v. Micron Technology Inc

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 2:25-cv-01010, E.D. Tex., 10/06/2025
  • Venue Allegations: Plaintiff alleges venue is proper for the Micron defendants based on their regular and established places of business in the Eastern District of Texas, including offices in Allen, Texas, where acts of patent infringement are alleged to have occurred. Venue for Avnet is alleged on a similar basis, with multiple regular and established places of business identified in Richardson and Plano, Texas.
  • Core Dispute: Plaintiff Yangtze Memory Technologies Company, Ltd. (YMTC) alleges that its direct competitor, Micron Technology, Inc., along with its distributor Avnet, Inc., infringes eight U.S. patents related to the design, manufacture, and operation of 3D NAND and DRAM semiconductor memory devices.
  • Technical Context: The lawsuit concerns foundational technologies in the highly competitive market for semiconductor memory, including advanced 3D NAND flash and Double Data Rate (DDR) DRAM, which are critical components in virtually all modern electronic devices.
  • Key Procedural History: The complaint alleges that Micron had knowledge of YMTC's patent portfolio prior to the lawsuit, noting that numerous YMTC-owned patents are cited on the face of Micron's own patents. No other significant procedural events, such as prior litigation involving the asserted patents or administrative validity challenges, are mentioned in the complaint.

Case Timeline

Date Event
2019-05-05 ’851 Patent Priority Date
2019-12-24 ’250 Patent Priority Date
2020-02-01 Accused Product Launch (LPDDR5)
2020-04-27 ’066 Patent Priority Date
2020-05-06 ’925 Patent Priority Date
2020-05-22 ’313 Patent Priority Date
2020-07-07 ’851 Patent Issue Date
2020-10-20 Accused Product Launch (uMCP5 with LPDDR5)
2021-05-17 ’403 Patent Priority Date
2021-05-28 ’621 Patent Priority Date
2021-12-22 ’767 Patent Priority Date
2022-01-25 ’066 Patent Issue Date
2024-08-20 ’250 Patent Issue Date
2024-08-27 ’621 Patent Issue Date
2024-09-17 ’767 Patent Issue Date
2025-02-18 ’313 Patent Issue Date
2025-03-18 ’925 Patent Issue Date
2025-04-01 ’403 Patent Issue Date
2025-10-06 Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 11,233,066 - “Three-Dimensional Memory Device and Method for Forming the Same”

  • Patent Identification: U.S. Patent No. 11,233,066, titled “Three-Dimensional Memory Device and Method for Forming the Same,” issued on January 25, 2022 (Compl. ¶46).

The Invention Explained

  • Problem Addressed: The patent background describes the need for 3D memory architectures to overcome the density limitations inherent in traditional planar memory cell designs (Compl. ¶48; ’066 Patent, col. 1:30-31).
  • The Patented Solution: The invention is a specific 3D memory device architecture. It comprises an N-type doped region on a substrate, an N-type doped semiconductor layer above it, and a memory stack built on top. A key feature is the "source contact structure" that extends vertically through the stack and into the doped region. The patent claims a specific geometry where the lateral dimension of this contact structure is greater in the portion surrounded by the N-type doped region than in the portion surrounded by the memory stack, creating a flared base for the contact (’066 Patent, Abstract; col. 1:39-52). This structure is depicted in Figure 1 of the patent, showing the relationship between the substrate (102), semiconductor layer (104), memory stack (106), and the source contact structure (122) with its wider lower portion (132).
  • Technical Importance: This architectural approach is intended to improve the electrical properties and structural integrity of the source connection in a dense, vertically integrated memory device, which may contribute to enhanced performance and manufacturing yield (Compl. ¶45).

Key Claims at a Glance

  • The complaint asserts independent claim 1 (Compl. ¶94).
  • Essential elements of claim 1 include:
    • An N-type doped region of a substrate with an N-type doped semiconductor layer thereon.
    • A memory stack of interleaved conductive and dielectric layers on the semiconductor layer.
    • A channel structure and a source contact structure, both extending vertically through the stack and semiconductor layer into the doped region.
    • A requirement that two different lateral dimensions of the source contact structure portion within the doped region are greater than a lateral dimension of the portion within the memory stack.
  • The complaint does not explicitly reserve the right to assert other claims of this patent, but the prayer for relief requests judgment on "one or more claims of the Asserted Patents" (Compl. p. 84, ¶1).

U.S. Patent No. 12,068,250 - “3D NAND Memory Device and Method of Forming the Same”

  • Patent Identification: U.S. Patent No. 12,068,250, titled “3D NAND Memory Device and Method of Forming the Same,” issued on August 20, 2024 (Compl. ¶50).

The Invention Explained

  • Problem Addressed: As 3D NAND technology scales to higher layer counts (e.g., from 64 to 128 layers), the process of forming the necessary "stair-cased" electrical contacts becomes more time-consuming, and the longer word lines at the bottom of the stack can suffer from high resistance-capacitance (RC) delay, limiting performance (Compl. ¶53; ’250 Patent, col. 6:5-15).
  • The Patented Solution: The patent describes a semiconductor device architecture with two memory array regions positioned at "opposing sides of the stack." A connection region between these arrays contains two distinct staircases. Each of these staircases is further composed of two groups of stairs that have opposing step-down directions and converge at a shared stair (’250 Patent, Abstract; col. 1:34-48). This complex, dual-staircase structure is designed to provide more efficient electrical access to the word lines in a very dense 3D array, as illustrated in patent Figures 4A and 4B.
  • Technical Importance: This architecture aims to solve key scaling challenges in 3D NAND by reducing RC delay and potentially simplifying fabrication, thereby enabling higher memory density and performance (Compl. ¶53).

Key Claims at a Glance

  • The complaint asserts independent claim 1 (Compl. ¶121).
  • Essential elements of claim 1 include:
    • A stack of alternating word line and insulating layers.
    • First and second array regions positioned at opposing sides of the stack.
    • A first staircase and a second staircase formed between the array regions.
    • The first staircase has first stairs with a first step-down direction and second stairs with an opposite, second step-down direction.
    • Each of the stairs corresponds to a different word line layer.

U.S. Patent No. 12,094,767 - “Barrier Layers for Word Line Contacts in a Three-Dimensional NAND Memory and Fabrication Methods Thereof”

  • Patent Identification: U.S. Patent No. 12,094,767, "Barrier Layers for Word Line Contacts in a Three-Dimensional NAND Memory and Fabrication Methods Thereof," issued September 17, 2024 (Compl. ¶56).
  • Technology Synopsis: The patent addresses problems in forming word line contacts in high-density 3D NAND, where traditional etch-stop layers can be lost during processing or cause manufacturing defects. The proposed solution is a fabrication method that involves creating a staircase structure, a dividing wall, and then sequentially forming two distinct barrier layers on the staircase to better control the etching process for creating contacts (Compl. ¶¶58-59).
  • Asserted Claims: The complaint identifies claim 1 as infringed (Compl. ¶147).
  • Accused Features: The complaint accuses Micron’s 232L and 276L Accused Products, including the Micron 2550 SSD and 2650 SSD (Compl. ¶145).

U.S. Patent No. 12,075,621 - “Three-Dimensional Memory Device and Method for Forming the Same”

  • Patent Identification: U.S. Patent No. 12,075,621, "Three-Dimensional Memory Device and Method for Forming the Same," issued August 27, 2024 (Compl. ¶60).
  • Technology Synopsis: The patent discloses a 3D memory device architecture intended to solve technical problems associated with stacking semiconductor wafers. The claimed device includes a doped semiconductor layer, a stack, and a channel structure where the drain select gate line is in direct contact with the semiconductor channel, while the word lines are in direct contact with the memory film, and all of these conductive lines comprise the same material (Compl. ¶¶62-63).
  • Asserted Claims: The complaint identifies claim 1 as infringed (Compl. ¶172).
  • Accused Features: The complaint accuses certain 276L Accused Products, including the Micron 2650 SSD (Compl. ¶171).

U.S. Patent No. 12,232,313 - “Staircase Structure in Three-Dimensional Memory Device and Method for Forming the Same”

  • Patent Identification: U.S. Patent No. 12,232,313, "Staircase Structure in Three-Dimensional Memory Device and Method for Forming the Same," issued February 18, 2025 (Compl. ¶64).
  • Technology Synopsis: The technology relates to 3D NAND structure to address density limitations and RC delay. The solution involves a memory array divided by a staircase structure that itself contains a "staircase zone" and a "bridge structure." The staircase zone features pairs of staircases facing each other with alternating ascending and descending steps at different depths (Compl. ¶¶66-67).
  • Asserted Claims: The complaint identifies claim 1 as infringed (Compl. ¶195).
  • Accused Features: The complaint accuses Micron’s 232L and 276L Accused Products (Compl. ¶193).

U.S. Patent No. 12,266,403 - “Three-Dimensional NAND Memory and Fabrication Method Thereof”

  • Patent Identification: U.S. Patent No. 12,266,403, "Three-Dimensional NAND Memory and Fabrication Method Thereof," issued April 1, 2025 (Compl. ¶68).
  • Technology Synopsis: The patent addresses the challenge of a shrinking "process window" in manufacturing increasingly dense 3D memory. It discloses a method using an etch-stop layer to form a Gate Line Slit (GLS) trench that is wider than the subsequent GLS opening, which penetrates deeper into the substrate, providing better manufacturing control (Compl. ¶¶70-71).
  • Asserted Claims: The complaint identifies claim 1 as infringed (Compl. ¶221).
  • Accused Features: The complaint accuses the manufacturing process for Micron’s 276L Accused Products (Compl. ¶¶219-220).

U.S. Patent No. 12,254,925 - “Control Method and Controller of 3D NAND Flash”

  • Patent Identification: U.S. Patent No. 12,254,925, "Control Method and Controller of 3D NAND Flash," issued March 18, 2025 (Compl. ¶72).
  • Technology Synopsis: The technology relates to improving programming performance in multi-level cell (MLC/TCL/QCL) 3D NAND, where programming time is critical. The disclosed method involves adjusting the pulse widths of the programming voltage pulses during a programming stage, such as making later pulses wider than earlier pulses, to optimize the programming process (Compl. ¶¶74-76).
  • Asserted Claims: The complaint identifies claim 1 as infringed (Compl. ¶246).
  • Accused Features: The complaint accuses certain 176L Accused Products, including the Micron 2400 and 2450 SSDs (Compl. ¶245).

U.S. Patent No. 10,707,851 - “Double Data Rate Circuit and Data Generation Method Implementing Precise Duty Cycle Control”

  • Patent Identification: U.S. Patent No. 10,707,851, "Double Data Rate Circuit and Data Generation Method Implementing Precise Duty Cycle Control," issued July 7, 2020 (Compl. ¶78).
  • Technology Synopsis: The patent addresses the need for a precise 50% duty-cycle clock in Double Data Rate (DDR) memory circuits to ensure timing accuracy. The invention is a DDR circuit that uses a clock divider to generate four 90-degree out-of-phase clock signals and a multiplexer constructed with matched NAND gates to reduce data skew and enhance system performance by maintaining a precise duty cycle (’851 Patent, col. 1:22-35; Compl. ¶82).
  • Asserted Claims: The complaint identifies claim 1 as infringed (Compl. ¶270).
  • Accused Features: The complaint accuses Micron’s LPDDR5 and LPDDR5X DRAM products (Compl. ¶268).

III. The Accused Instrumentality

Product Identification

  • The complaint identifies five main categories of accused instrumentalities: 176-layer, 232-layer, and 276-layer 3D NAND devices, as well as Low-Power DDR5 and DDR5X DRAM devices (Compl. ¶84). Specific examples include Micron's 2400, 2450, 2550, and 2650 series of solid-state drives (SSDs) (Compl. ¶¶91, 119, 245).

Functionality and Market Context

  • The accused products are semiconductor memory components at the heart of the modern data economy. The complaint alleges these devices are used in a wide array of end-products, including mobile devices, consumer electronics, computers, servers, and data centers (Compl. ¶4). The complaint provides visual evidence from Micron's marketing materials, such as a snippet from a technical brief for the Micron 2550 SSD, which is described as the "World's First Client SSD From a NAND OEM With >200-Layer NAND" (Compl. p. 31). This positions the accused products at the forefront of the memory market. Plaintiff characterizes Micron as one of its "primary competitors in the NAND memory space" (Compl. ¶2).

IV. Analysis of Infringement Allegations

11,233,066 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
an N-type doped region of a substrate; an N-type doped semiconductor layer on the N-type doped region; The 232L and 276L Accused Products are alleged to include an N-type doped region of a substrate and an N-type doped semiconductor layer on that region. ¶98 col. 1:39-41
a memory stack comprising interleaved conductive layers and dielectric layers on the N-type doped semiconductor layer; The accused products allegedly contain a memory stack with interleaved conductive and dielectric layers. This is supported by reference to Micron's technical infographics for its G8 and G9 NAND. ¶98 col. 1:42-44
a channel structure extending vertically...and a source contact structure extending vertically...into the N-type doped region; On information and belief, the accused products contain channel and source contact structures that extend vertically through the memory stack into the doped region. ¶99 col. 1:44-49
a first lateral dimension of a first portion of the source contact structure surrounded by the N-type doped region is greater than a second lateral dimension of a second portion...surrounded by the memory stack; and a third lateral dimension...is greater than the second lateral dimension... On information and belief, the source contact structure in the accused products is wider in the portion surrounded by the doped region than in the portion surrounded by the memory stack. ¶99 col. 1:49-52
  • Identified Points of Contention:
    • Evidentiary Questions: The central infringement allegations concerning the specific geometry of the "source contact structure"—namely, that its base is wider than its upper portion—are pleaded "on information and belief" (Compl. ¶99). A primary point of contention will be factual and evidentiary: does physical analysis of Micron's 232L and 276L devices reveal a source contact structure with the specific dimensional characteristics required by claim 1?
    • Scope Questions: The term "lateral dimension" is recited without a specific axis or method of measurement. A potential dispute may arise over how this dimension is measured and at which specific points on the "first portion" and "second portion" of the source contact structure, and whether any variation in width in Micron's products meets the "greater than" limitation.

12,068,250 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
a stack of word line layers and insulating layers that are stacked alternatingly; The Micron 232L and 276L Accused Products are described as semiconductor devices that include a stack of alternatingly stacked word line and insulating layers. ¶125 col. 1:22-25
channel structures formed in a first array region and a second array region of the stack, the first array region and the second array region being positioned at opposing sides of the stack... On information and belief, the accused products include channel structures formed in two array regions located on opposing sides of the device's memory stack. ¶126 col. 1:24-27
a first staircase is formed between the first array region and the second array region, a second staircase is formed between the first array region and the second array region... On information and belief, the accused products include a first staircase and a second staircase situated between the two array regions. ¶126 col. 1:35-39
the first staircase has first stairs with a first step-down direction and second stairs with a second step-down direction, the first step-down direction being opposite to the second step-down direction... On information and belief, the first staircase in the accused products is itself comprised of stairs having opposing step-down directions. ¶126 col. 1:45-48
  • Identified Points of Contention:
    • Evidentiary Questions: Similar to the '066 patent, the allegations regarding the complex, multi-part staircase architecture are made "on information and belief" (Compl. ¶126). The key question will be whether discovery and reverse engineering of Micron's products reveal a structure with two separate staircases, each of which is itself composed of stairs with opposing step-down directions. The complaint's reference to a Micron product brief stating its 232-layer NAND has "an independent wordline on each of these six planes" may be an initial piece of evidence toward this complex structure (Compl. ¶125).
    • Scope Questions: A central issue for claim construction may be the definition of "a first staircase." The claim language defines "a first staircase" as itself comprising stairs with opposing directions. This raises the question of whether "a first staircase" is a single, unitary structure with an overall V-shape (as depicted in the patent's figures) or if it can be read more broadly. The resolution of this term's scope will be critical to determining infringement.

V. Key Claim Terms for Construction

  • Patent: U.S. Patent No. 11,233,066

    • The Term: "source contact structure"
    • Context and Importance: The infringement theory for the '066 Patent turns entirely on the specific geometry of this structure, particularly the "greater than" dimensional limitation. Its definition will determine whether the physical structure of Micron's devices infringes. Practitioners may focus on this term because the complaint's allegations regarding its specific shape are based on "information and belief," suggesting this will be a heavily contested factual and legal issue.
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation: The specification describes the structure as potentially being an "array common source (ACS) of multiple NAND memory strings" (’066 Patent, col. 7:59-8:4), which might support a more functional definition based on its role in the circuit rather than its precise shape.
      • Evidence for a Narrower Interpretation: The abstract explicitly describes the dimensional limitation, stating "a first lateral dimension of a first portion...is greater than a second lateral dimension of a second portion" (’066 Patent, Abstract). Figures like FIG. 1 (showing flared portion 132 relative to upper portion 134) and the summary of the invention consistently emphasize this specific geometry, which may support limiting the term to a structure with this flared or enlarged base.

  • Patent: U.S. Patent No. 12,068,250

    • The Term: "a first staircase"
    • Context and Importance: Claim 1 requires "a first staircase" and "a second staircase," where the "first staircase" is itself defined as having stairs with opposing step-down directions. The definition of a single "staircase" is therefore fundamental to understanding the claimed architecture and whether Micron's products infringe.
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation: The term "staircase" is used generally in the background to refer to the stepped configuration needed to access word lines in 3D NAND (’250 Patent, col. 6:5-15). This could support an argument that the term should be given its plain and ordinary meaning in the art, with the subsequent limitations defining its specific required form.
      • Evidence for a Narrower Interpretation: The claim language itself gives the term "a first staircase" a specific structure: "the first staircase has first stairs with a first step-down direction and second stairs with a second step-down direction, the first step-down direction being opposite to the second." This suggests "a first staircase" is not a simple linear structure but a compound one. Embodiments like FIG. 4A, which labels the entire V-shaped structure formed by stairs 402A and 402B as "first staircase 402," may support an argument that the term requires this specific converging, dual-direction configuration.

VI. Other Allegations

  • Indirect Infringement: The complaint alleges both induced and contributory infringement for all asserted patents. Inducement allegations are based on Micron's and Avnet's advertising, product briefs, technical specifications, and other instructional materials that allegedly encourage and instruct customers to use the accused products in an infringing manner (e.g., Compl. ¶¶102-107, 129-134). Contributory infringement is alleged on the basis that the accused products are especially designed to practice the patented inventions and have no substantial non-infringing uses (e.g., Compl. ¶¶108-109, 135-136).
  • Willful Infringement: The complaint alleges willful infringement for all asserted patents. The basis for willfulness includes both post-suit knowledge (from the filing of the complaint) and, more significantly, alleged pre-suit knowledge. The pre-suit knowledge allegation is based on the claim that "Many YMTC-owned patents are cited on the face of Micron's own patents," which purportedly demonstrates Micron's awareness of YMTC's relevant patent portfolio before the lawsuit was filed (Compl. ¶89).

VII. Analyst’s Conclusion: Key Questions for the Case

  • A central issue for the NAND patents will be evidentiary and structural: can YMTC prove through reverse engineering and discovery that Micron’s high-volume commercial products embody the specific and complex 3D architectures claimed in the patents, such as the flared “source contact structure” of the ’066 patent or the dual, opposing-direction “staircases” of the ’250 patent, particularly where these allegations are currently based on "information and belief"?
  • The case will also turn on a question of definitional scope and claim construction, especially for the structural patents. For example, can the term “a first staircase” in the ’250 patent, which the claim itself defines as having stairs with opposing directions, be construed to cover anything other than the unitary, V-shaped structure depicted in the patent’s figures? The construction of such terms will be dispositive for infringement.
  • A key question regarding damages will be one of pre-suit knowledge and willfulness: will the allegation that YMTC’s patents were cited as prior art during the prosecution of Micron's own patents be sufficient to establish that Micron knew of the asserted patents or was willfully blind to the risk of infringement, potentially opening the door to enhanced damages?